IB/mlx4: Use multiple WQ blocks to post smaller send WQEs
ConnectX HCA supports shrinking WQEs, so that a single work request can be made of multiple units of wqe_shift. This way, WRs can differ in size, and do not have to be a power of 2 in size, saving memory and speeding up send WR posting. Unfortunately, if we do this then the wqe_index field in CQEs can't be used to look up the WR ID anymore, so our implementation does this only if selective signaling is off. Further, on 32-bit platforms, we can't use vmap() to make the QP buffer virtually contigious. Thus we have to use constant-sized WRs to make sure a WR is always fully within a single page-sized chunk. Finally, we use WRs with the NOP opcode to avoid wrapping around the queue buffer in the middle of posting a WR, and we set the NoErrorCompletion bit to avoid getting completions with error for NOP WRs. However, NEC is only supported starting with firmware 2.2.232, so we use constant-sized WRs for older firmware. And, since MLX QPs only support SEND, we use constant-sized WRs in this case. When stamping during NOP posting, do stamping following setting of the NOP WQE valid bit. Signed-off-by: Michael S. Tsirkin <mst@dev.mellanox.co.il> Signed-off-by: Jack Morgenstein <jackm@dev.mellanox.co.il> Signed-off-by: Roland Dreier <rolandd@cisco.com>
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Roland Dreier
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@ -133,6 +133,11 @@ enum {
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MLX4_STAT_RATE_OFFSET = 5
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};
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static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor)
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{
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return (major << 32) | (minor << 16) | subminor;
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}
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struct mlx4_caps {
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u64 fw_ver;
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int num_ports;
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@ -154,7 +154,11 @@ struct mlx4_qp_context {
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u32 reserved5[10];
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};
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/* Which firmware version adds support for NEC (NoErrorCompletion) bit */
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#define MLX4_FW_VER_WQE_CTRL_NEC mlx4_fw_ver(2, 2, 232)
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enum {
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MLX4_WQE_CTRL_NEC = 1 << 29,
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MLX4_WQE_CTRL_FENCE = 1 << 6,
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MLX4_WQE_CTRL_CQ_UPDATE = 3 << 2,
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MLX4_WQE_CTRL_SOLICITED = 1 << 1,
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