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netxen: cache align register map table

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Aligning register offset translation table imporves performance
on rx side.

Signed-off-by: Dhananjay Phadke <dhananjay@netxen.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Dhananjay Phadke
2009-04-07 22:50:48 +00:00
committed by David S. Miller
parent a92e9e65f0
commit ea7eaa39ff
1 changed files with 2 additions and 1 deletions
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3
drivers/net/netxen/netxen_nic_hw.c
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@@ -89,7 +89,8 @@ static void __iomem *pci_base_offset(struct netxen_adapter *adapter,
} }
#define CRB_WIN_LOCK_TIMEOUT 100000000 #define CRB_WIN_LOCK_TIMEOUT 100000000
static crb_128M_2M_block_map_t crb_128M_2M_map[64] = { static crb_128M_2M_block_map_t
crb_128M_2M_map[64] __cacheline_aligned_in_smp = {
{{{0, 0, 0, 0} } }, /* 0: PCI */ {{{0, 0, 0, 0} } }, /* 0: PCI */
{{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */ {{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */
{1, 0x0110000, 0x0120000, 0x130000}, {1, 0x0110000, 0x0120000, 0x130000},