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arch/tile: factor out <arch/opcode.h> header

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The kernel code was using some <asm> headers that included a mix
of hardware-specific information (typically found in Tilera <arch>
headers) and structures, enums, and function declarations supporting
the disassembly function of the tile-desc.c sources.

This change refactors that code so that a hardware-specific, but
OS- and application-agnostic header, is created: <arch/opcode.h>.
This header is then exported to userspace along with the other
<arch> headers and can be used to build userspace code; in particular,
it is used by glibc as part of implementing the backtrace() function.

The new header, together with a header that specifically describes
the disassembly code (<asm/tile-desc.h> with _32 and _64 variants),
replaces the old <asm/opcode-tile*.h> and <asm/opcode_constants*.h>
headers.

As part of this change, we are also renaming the 32-bit constants
from TILE_xxx to TILEPRO_xxx to better reflect the fact that they
are specific to the TILEPro architecture, and not to TILE-Gx
and any successor "tile" architecture chips.

Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
This commit is contained in:
Chris Metcalf
2011-11-02 23:02:17 -04:00
parent aeddea5d37
commit eb7c792da5
15 changed files with 4536 additions and 4359 deletions
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30
arch/tile/include/asm/opcode-tile.h
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/*
* Copyright 2010 Tilera Corporation. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation, version 2.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
* NON INFRINGEMENT. See the GNU General Public License for
* more details.
*/
#ifndef _ASM_TILE_OPCODE_TILE_H
#define _ASM_TILE_OPCODE_TILE_H
#include <arch/chip.h>
#if CHIP_WORD_SIZE() == 64
#include <asm/opcode-tile_64.h>
#else
#include <asm/opcode-tile_32.h>
#endif
/* These definitions are not correct for TILE64, so just avoid them. */
#undef TILE_ELF_MACHINE_CODE
#undef TILE_ELF_NAME
#endif /* _ASM_TILE_OPCODE_TILE_H */

1513
arch/tile/include/asm/opcode-tile_32.h
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1248
arch/tile/include/asm/opcode-tile_64.h
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480
arch/tile/include/asm/opcode_constants_32.h
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/*
* Copyright 2010 Tilera Corporation. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation, version 2.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
* NON INFRINGEMENT. See the GNU General Public License for
* more details.
*/
/* This file is machine-generated; DO NOT EDIT! */
#ifndef _TILE_OPCODE_CONSTANTS_H
#define _TILE_OPCODE_CONSTANTS_H
enum
{
ADDBS_U_SPECIAL_0_OPCODE_X0 = 98,
ADDBS_U_SPECIAL_0_OPCODE_X1 = 68,
ADDB_SPECIAL_0_OPCODE_X0 = 1,
ADDB_SPECIAL_0_OPCODE_X1 = 1,
ADDHS_SPECIAL_0_OPCODE_X0 = 99,
ADDHS_SPECIAL_0_OPCODE_X1 = 69,
ADDH_SPECIAL_0_OPCODE_X0 = 2,
ADDH_SPECIAL_0_OPCODE_X1 = 2,
ADDIB_IMM_0_OPCODE_X0 = 1,
ADDIB_IMM_0_OPCODE_X1 = 1,
ADDIH_IMM_0_OPCODE_X0 = 2,
ADDIH_IMM_0_OPCODE_X1 = 2,
ADDI_IMM_0_OPCODE_X0 = 3,
ADDI_IMM_0_OPCODE_X1 = 3,
ADDI_IMM_1_OPCODE_SN = 1,
ADDI_OPCODE_Y0 = 9,
ADDI_OPCODE_Y1 = 7,
ADDLIS_OPCODE_X0 = 1,
ADDLIS_OPCODE_X1 = 2,
ADDLI_OPCODE_X0 = 2,
ADDLI_OPCODE_X1 = 3,
ADDS_SPECIAL_0_OPCODE_X0 = 96,
ADDS_SPECIAL_0_OPCODE_X1 = 66,
ADD_SPECIAL_0_OPCODE_X0 = 3,
ADD_SPECIAL_0_OPCODE_X1 = 3,
ADD_SPECIAL_0_OPCODE_Y0 = 0,
ADD_SPECIAL_0_OPCODE_Y1 = 0,
ADIFFB_U_SPECIAL_0_OPCODE_X0 = 4,
ADIFFH_SPECIAL_0_OPCODE_X0 = 5,
ANDI_IMM_0_OPCODE_X0 = 1,
ANDI_IMM_0_OPCODE_X1 = 4,
ANDI_OPCODE_Y0 = 10,
ANDI_OPCODE_Y1 = 8,
AND_SPECIAL_0_OPCODE_X0 = 6,
AND_SPECIAL_0_OPCODE_X1 = 4,
AND_SPECIAL_2_OPCODE_Y0 = 0,
AND_SPECIAL_2_OPCODE_Y1 = 0,
AULI_OPCODE_X0 = 3,
AULI_OPCODE_X1 = 4,
AVGB_U_SPECIAL_0_OPCODE_X0 = 7,
AVGH_SPECIAL_0_OPCODE_X0 = 8,
BBNST_BRANCH_OPCODE_X1 = 15,
BBNS_BRANCH_OPCODE_X1 = 14,
BBNS_OPCODE_SN = 63,
BBST_BRANCH_OPCODE_X1 = 13,
BBS_BRANCH_OPCODE_X1 = 12,
BBS_OPCODE_SN = 62,
BGEZT_BRANCH_OPCODE_X1 = 7,
BGEZ_BRANCH_OPCODE_X1 = 6,
BGEZ_OPCODE_SN = 61,
BGZT_BRANCH_OPCODE_X1 = 5,
BGZ_BRANCH_OPCODE_X1 = 4,
BGZ_OPCODE_SN = 58,
BITX_UN_0_SHUN_0_OPCODE_X0 = 1,
BITX_UN_0_SHUN_0_OPCODE_Y0 = 1,
BLEZT_BRANCH_OPCODE_X1 = 11,
BLEZ_BRANCH_OPCODE_X1 = 10,
BLEZ_OPCODE_SN = 59,
BLZT_BRANCH_OPCODE_X1 = 9,
BLZ_BRANCH_OPCODE_X1 = 8,
BLZ_OPCODE_SN = 60,
BNZT_BRANCH_OPCODE_X1 = 3,
BNZ_BRANCH_OPCODE_X1 = 2,
BNZ_OPCODE_SN = 57,
BPT_NOREG_RR_IMM_0_OPCODE_SN = 1,
BRANCH_OPCODE_X1 = 5,
BYTEX_UN_0_SHUN_0_OPCODE_X0 = 2,
BYTEX_UN_0_SHUN_0_OPCODE_Y0 = 2,
BZT_BRANCH_OPCODE_X1 = 1,
BZ_BRANCH_OPCODE_X1 = 0,
BZ_OPCODE_SN = 56,
CLZ_UN_0_SHUN_0_OPCODE_X0 = 3,
CLZ_UN_0_SHUN_0_OPCODE_Y0 = 3,
CRC32_32_SPECIAL_0_OPCODE_X0 = 9,
CRC32_8_SPECIAL_0_OPCODE_X0 = 10,
CTZ_UN_0_SHUN_0_OPCODE_X0 = 4,
CTZ_UN_0_SHUN_0_OPCODE_Y0 = 4,
DRAIN_UN_0_SHUN_0_OPCODE_X1 = 1,
DTLBPR_UN_0_SHUN_0_OPCODE_X1 = 2,
DWORD_ALIGN_SPECIAL_0_OPCODE_X0 = 95,
FINV_UN_0_SHUN_0_OPCODE_X1 = 3,
FLUSH_UN_0_SHUN_0_OPCODE_X1 = 4,
FNOP_NOREG_RR_IMM_0_OPCODE_SN = 3,
FNOP_UN_0_SHUN_0_OPCODE_X0 = 5,
FNOP_UN_0_SHUN_0_OPCODE_X1 = 5,
FNOP_UN_0_SHUN_0_OPCODE_Y0 = 5,
FNOP_UN_0_SHUN_0_OPCODE_Y1 = 1,
HALT_NOREG_RR_IMM_0_OPCODE_SN = 0,
ICOH_UN_0_SHUN_0_OPCODE_X1 = 6,
ILL_UN_0_SHUN_0_OPCODE_X1 = 7,
ILL_UN_0_SHUN_0_OPCODE_Y1 = 2,
IMM_0_OPCODE_SN = 0,
IMM_0_OPCODE_X0 = 4,
IMM_0_OPCODE_X1 = 6,
IMM_1_OPCODE_SN = 1,
IMM_OPCODE_0_X0 = 5,
INTHB_SPECIAL_0_OPCODE_X0 = 11,
INTHB_SPECIAL_0_OPCODE_X1 = 5,
INTHH_SPECIAL_0_OPCODE_X0 = 12,
INTHH_SPECIAL_0_OPCODE_X1 = 6,
INTLB_SPECIAL_0_OPCODE_X0 = 13,
INTLB_SPECIAL_0_OPCODE_X1 = 7,
INTLH_SPECIAL_0_OPCODE_X0 = 14,
INTLH_SPECIAL_0_OPCODE_X1 = 8,
INV_UN_0_SHUN_0_OPCODE_X1 = 8,
IRET_UN_0_SHUN_0_OPCODE_X1 = 9,
JALB_OPCODE_X1 = 13,
JALF_OPCODE_X1 = 12,
JALRP_SPECIAL_0_OPCODE_X1 = 9,
JALRR_IMM_1_OPCODE_SN = 3,
JALR_RR_IMM_0_OPCODE_SN = 5,
JALR_SPECIAL_0_OPCODE_X1 = 10,
JB_OPCODE_X1 = 11,
JF_OPCODE_X1 = 10,
JRP_SPECIAL_0_OPCODE_X1 = 11,
JRR_IMM_1_OPCODE_SN = 2,
JR_RR_IMM_0_OPCODE_SN = 4,
JR_SPECIAL_0_OPCODE_X1 = 12,
LBADD_IMM_0_OPCODE_X1 = 22,
LBADD_U_IMM_0_OPCODE_X1 = 23,
LB_OPCODE_Y2 = 0,
LB_UN_0_SHUN_0_OPCODE_X1 = 10,
LB_U_OPCODE_Y2 = 1,
LB_U_UN_0_SHUN_0_OPCODE_X1 = 11,
LHADD_IMM_0_OPCODE_X1 = 24,
LHADD_U_IMM_0_OPCODE_X1 = 25,
LH_OPCODE_Y2 = 2,
LH_UN_0_SHUN_0_OPCODE_X1 = 12,
LH_U_OPCODE_Y2 = 3,
LH_U_UN_0_SHUN_0_OPCODE_X1 = 13,
LNK_SPECIAL_0_OPCODE_X1 = 13,
LWADD_IMM_0_OPCODE_X1 = 26,
LWADD_NA_IMM_0_OPCODE_X1 = 27,
LW_NA_UN_0_SHUN_0_OPCODE_X1 = 24,
LW_OPCODE_Y2 = 4,
LW_UN_0_SHUN_0_OPCODE_X1 = 14,
MAXB_U_SPECIAL_0_OPCODE_X0 = 15,
MAXB_U_SPECIAL_0_OPCODE_X1 = 14,
MAXH_SPECIAL_0_OPCODE_X0 = 16,
MAXH_SPECIAL_0_OPCODE_X1 = 15,
MAXIB_U_IMM_0_OPCODE_X0 = 4,
MAXIB_U_IMM_0_OPCODE_X1 = 5,
MAXIH_IMM_0_OPCODE_X0 = 5,
MAXIH_IMM_0_OPCODE_X1 = 6,
MFSPR_IMM_0_OPCODE_X1 = 7,
MF_UN_0_SHUN_0_OPCODE_X1 = 15,
MINB_U_SPECIAL_0_OPCODE_X0 = 17,
MINB_U_SPECIAL_0_OPCODE_X1 = 16,
MINH_SPECIAL_0_OPCODE_X0 = 18,
MINH_SPECIAL_0_OPCODE_X1 = 17,
MINIB_U_IMM_0_OPCODE_X0 = 6,
MINIB_U_IMM_0_OPCODE_X1 = 8,
MINIH_IMM_0_OPCODE_X0 = 7,
MINIH_IMM_0_OPCODE_X1 = 9,
MM_OPCODE_X0 = 6,
MM_OPCODE_X1 = 7,
MNZB_SPECIAL_0_OPCODE_X0 = 19,
MNZB_SPECIAL_0_OPCODE_X1 = 18,
MNZH_SPECIAL_0_OPCODE_X0 = 20,
MNZH_SPECIAL_0_OPCODE_X1 = 19,
MNZ_SPECIAL_0_OPCODE_X0 = 21,
MNZ_SPECIAL_0_OPCODE_X1 = 20,
MNZ_SPECIAL_1_OPCODE_Y0 = 0,
MNZ_SPECIAL_1_OPCODE_Y1 = 1,
MOVEI_IMM_1_OPCODE_SN = 0,
MOVE_RR_IMM_0_OPCODE_SN = 8,
MTSPR_IMM_0_OPCODE_X1 = 10,
MULHHA_SS_SPECIAL_0_OPCODE_X0 = 22,
MULHHA_SS_SPECIAL_7_OPCODE_Y0 = 0,
MULHHA_SU_SPECIAL_0_OPCODE_X0 = 23,
MULHHA_UU_SPECIAL_0_OPCODE_X0 = 24,
MULHHA_UU_SPECIAL_7_OPCODE_Y0 = 1,
MULHHSA_UU_SPECIAL_0_OPCODE_X0 = 25,
MULHH_SS_SPECIAL_0_OPCODE_X0 = 26,
MULHH_SS_SPECIAL_6_OPCODE_Y0 = 0,
MULHH_SU_SPECIAL_0_OPCODE_X0 = 27,
MULHH_UU_SPECIAL_0_OPCODE_X0 = 28,
MULHH_UU_SPECIAL_6_OPCODE_Y0 = 1,
MULHLA_SS_SPECIAL_0_OPCODE_X0 = 29,
MULHLA_SU_SPECIAL_0_OPCODE_X0 = 30,
MULHLA_US_SPECIAL_0_OPCODE_X0 = 31,
MULHLA_UU_SPECIAL_0_OPCODE_X0 = 32,
MULHLSA_UU_SPECIAL_0_OPCODE_X0 = 33,
MULHLSA_UU_SPECIAL_5_OPCODE_Y0 = 0,
MULHL_SS_SPECIAL_0_OPCODE_X0 = 34,
MULHL_SU_SPECIAL_0_OPCODE_X0 = 35,
MULHL_US_SPECIAL_0_OPCODE_X0 = 36,
MULHL_UU_SPECIAL_0_OPCODE_X0 = 37,
MULLLA_SS_SPECIAL_0_OPCODE_X0 = 38,
MULLLA_SS_SPECIAL_7_OPCODE_Y0 = 2,
MULLLA_SU_SPECIAL_0_OPCODE_X0 = 39,
MULLLA_UU_SPECIAL_0_OPCODE_X0 = 40,
MULLLA_UU_SPECIAL_7_OPCODE_Y0 = 3,
MULLLSA_UU_SPECIAL_0_OPCODE_X0 = 41,
MULLL_SS_SPECIAL_0_OPCODE_X0 = 42,
MULLL_SS_SPECIAL_6_OPCODE_Y0 = 2,
MULLL_SU_SPECIAL_0_OPCODE_X0 = 43,
MULLL_UU_SPECIAL_0_OPCODE_X0 = 44,
MULLL_UU_SPECIAL_6_OPCODE_Y0 = 3,
MVNZ_SPECIAL_0_OPCODE_X0 = 45,
MVNZ_SPECIAL_1_OPCODE_Y0 = 1,
MVZ_SPECIAL_0_OPCODE_X0 = 46,
MVZ_SPECIAL_1_OPCODE_Y0 = 2,
MZB_SPECIAL_0_OPCODE_X0 = 47,
MZB_SPECIAL_0_OPCODE_X1 = 21,
MZH_SPECIAL_0_OPCODE_X0 = 48,
MZH_SPECIAL_0_OPCODE_X1 = 22,
MZ_SPECIAL_0_OPCODE_X0 = 49,
MZ_SPECIAL_0_OPCODE_X1 = 23,
MZ_SPECIAL_1_OPCODE_Y0 = 3,
MZ_SPECIAL_1_OPCODE_Y1 = 2,
NAP_UN_0_SHUN_0_OPCODE_X1 = 16,
NOP_NOREG_RR_IMM_0_OPCODE_SN = 2,
NOP_UN_0_SHUN_0_OPCODE_X0 = 6,
NOP_UN_0_SHUN_0_OPCODE_X1 = 17,
NOP_UN_0_SHUN_0_OPCODE_Y0 = 6,
NOP_UN_0_SHUN_0_OPCODE_Y1 = 3,
NOREG_RR_IMM_0_OPCODE_SN = 0,
NOR_SPECIAL_0_OPCODE_X0 = 50,
NOR_SPECIAL_0_OPCODE_X1 = 24,
NOR_SPECIAL_2_OPCODE_Y0 = 1,
NOR_SPECIAL_2_OPCODE_Y1 = 1,
ORI_IMM_0_OPCODE_X0 = 8,
ORI_IMM_0_OPCODE_X1 = 11,
ORI_OPCODE_Y0 = 11,
ORI_OPCODE_Y1 = 9,
OR_SPECIAL_0_OPCODE_X0 = 51,
OR_SPECIAL_0_OPCODE_X1 = 25,
OR_SPECIAL_2_OPCODE_Y0 = 2,
OR_SPECIAL_2_OPCODE_Y1 = 2,
PACKBS_U_SPECIAL_0_OPCODE_X0 = 103,
PACKBS_U_SPECIAL_0_OPCODE_X1 = 73,
PACKHB_SPECIAL_0_OPCODE_X0 = 52,
PACKHB_SPECIAL_0_OPCODE_X1 = 26,
PACKHS_SPECIAL_0_OPCODE_X0 = 102,
PACKHS_SPECIAL_0_OPCODE_X1 = 72,
PACKLB_SPECIAL_0_OPCODE_X0 = 53,
PACKLB_SPECIAL_0_OPCODE_X1 = 27,
PCNT_UN_0_SHUN_0_OPCODE_X0 = 7,
PCNT_UN_0_SHUN_0_OPCODE_Y0 = 7,
RLI_SHUN_0_OPCODE_X0 = 1,
RLI_SHUN_0_OPCODE_X1 = 1,
RLI_SHUN_0_OPCODE_Y0 = 1,
RLI_SHUN_0_OPCODE_Y1 = 1,
RL_SPECIAL_0_OPCODE_X0 = 54,
RL_SPECIAL_0_OPCODE_X1 = 28,
RL_SPECIAL_3_OPCODE_Y0 = 0,
RL_SPECIAL_3_OPCODE_Y1 = 0,
RR_IMM_0_OPCODE_SN = 0,
S1A_SPECIAL_0_OPCODE_X0 = 55,
S1A_SPECIAL_0_OPCODE_X1 = 29,
S1A_SPECIAL_0_OPCODE_Y0 = 1,
S1A_SPECIAL_0_OPCODE_Y1 = 1,
S2A_SPECIAL_0_OPCODE_X0 = 56,
S2A_SPECIAL_0_OPCODE_X1 = 30,
S2A_SPECIAL_0_OPCODE_Y0 = 2,
S2A_SPECIAL_0_OPCODE_Y1 = 2,
S3A_SPECIAL_0_OPCODE_X0 = 57,
S3A_SPECIAL_0_OPCODE_X1 = 31,
S3A_SPECIAL_5_OPCODE_Y0 = 1,
S3A_SPECIAL_5_OPCODE_Y1 = 1,
SADAB_U_SPECIAL_0_OPCODE_X0 = 58,
SADAH_SPECIAL_0_OPCODE_X0 = 59,
SADAH_U_SPECIAL_0_OPCODE_X0 = 60,
SADB_U_SPECIAL_0_OPCODE_X0 = 61,
SADH_SPECIAL_0_OPCODE_X0 = 62,
SADH_U_SPECIAL_0_OPCODE_X0 = 63,
SBADD_IMM_0_OPCODE_X1 = 28,
SB_OPCODE_Y2 = 5,
SB_SPECIAL_0_OPCODE_X1 = 32,
SEQB_SPECIAL_0_OPCODE_X0 = 64,
SEQB_SPECIAL_0_OPCODE_X1 = 33,
SEQH_SPECIAL_0_OPCODE_X0 = 65,
SEQH_SPECIAL_0_OPCODE_X1 = 34,
SEQIB_IMM_0_OPCODE_X0 = 9,
SEQIB_IMM_0_OPCODE_X1 = 12,
SEQIH_IMM_0_OPCODE_X0 = 10,
SEQIH_IMM_0_OPCODE_X1 = 13,
SEQI_IMM_0_OPCODE_X0 = 11,
SEQI_IMM_0_OPCODE_X1 = 14,
SEQI_OPCODE_Y0 = 12,
SEQI_OPCODE_Y1 = 10,
SEQ_SPECIAL_0_OPCODE_X0 = 66,
SEQ_SPECIAL_0_OPCODE_X1 = 35,
SEQ_SPECIAL_5_OPCODE_Y0 = 2,
SEQ_SPECIAL_5_OPCODE_Y1 = 2,
SHADD_IMM_0_OPCODE_X1 = 29,
SHL8II_IMM_0_OPCODE_SN = 3,
SHLB_SPECIAL_0_OPCODE_X0 = 67,
SHLB_SPECIAL_0_OPCODE_X1 = 36,
SHLH_SPECIAL_0_OPCODE_X0 = 68,
SHLH_SPECIAL_0_OPCODE_X1 = 37,
SHLIB_SHUN_0_OPCODE_X0 = 2,
SHLIB_SHUN_0_OPCODE_X1 = 2,
SHLIH_SHUN_0_OPCODE_X0 = 3,
SHLIH_SHUN_0_OPCODE_X1 = 3,
SHLI_SHUN_0_OPCODE_X0 = 4,
SHLI_SHUN_0_OPCODE_X1 = 4,
SHLI_SHUN_0_OPCODE_Y0 = 2,
SHLI_SHUN_0_OPCODE_Y1 = 2,
SHL_SPECIAL_0_OPCODE_X0 = 69,
SHL_SPECIAL_0_OPCODE_X1 = 38,
SHL_SPECIAL_3_OPCODE_Y0 = 1,
SHL_SPECIAL_3_OPCODE_Y1 = 1,
SHR1_RR_IMM_0_OPCODE_SN = 9,
SHRB_SPECIAL_0_OPCODE_X0 = 70,
SHRB_SPECIAL_0_OPCODE_X1 = 39,
SHRH_SPECIAL_0_OPCODE_X0 = 71,
SHRH_SPECIAL_0_OPCODE_X1 = 40,
SHRIB_SHUN_0_OPCODE_X0 = 5,
SHRIB_SHUN_0_OPCODE_X1 = 5,
SHRIH_SHUN_0_OPCODE_X0 = 6,
SHRIH_SHUN_0_OPCODE_X1 = 6,
SHRI_SHUN_0_OPCODE_X0 = 7,
SHRI_SHUN_0_OPCODE_X1 = 7,
SHRI_SHUN_0_OPCODE_Y0 = 3,
SHRI_SHUN_0_OPCODE_Y1 = 3,
SHR_SPECIAL_0_OPCODE_X0 = 72,
SHR_SPECIAL_0_OPCODE_X1 = 41,
SHR_SPECIAL_3_OPCODE_Y0 = 2,
SHR_SPECIAL_3_OPCODE_Y1 = 2,
SHUN_0_OPCODE_X0 = 7,
SHUN_0_OPCODE_X1 = 8,
SHUN_0_OPCODE_Y0 = 13,
SHUN_0_OPCODE_Y1 = 11,
SH_OPCODE_Y2 = 6,
SH_SPECIAL_0_OPCODE_X1 = 42,
SLTB_SPECIAL_0_OPCODE_X0 = 73,
SLTB_SPECIAL_0_OPCODE_X1 = 43,
SLTB_U_SPECIAL_0_OPCODE_X0 = 74,
SLTB_U_SPECIAL_0_OPCODE_X1 = 44,
SLTEB_SPECIAL_0_OPCODE_X0 = 75,
SLTEB_SPECIAL_0_OPCODE_X1 = 45,
SLTEB_U_SPECIAL_0_OPCODE_X0 = 76,
SLTEB_U_SPECIAL_0_OPCODE_X1 = 46,
SLTEH_SPECIAL_0_OPCODE_X0 = 77,
SLTEH_SPECIAL_0_OPCODE_X1 = 47,
SLTEH_U_SPECIAL_0_OPCODE_X0 = 78,
SLTEH_U_SPECIAL_0_OPCODE_X1 = 48,
SLTE_SPECIAL_0_OPCODE_X0 = 79,
SLTE_SPECIAL_0_OPCODE_X1 = 49,
SLTE_SPECIAL_4_OPCODE_Y0 = 0,
SLTE_SPECIAL_4_OPCODE_Y1 = 0,
SLTE_U_SPECIAL_0_OPCODE_X0 = 80,
SLTE_U_SPECIAL_0_OPCODE_X1 = 50,
SLTE_U_SPECIAL_4_OPCODE_Y0 = 1,
SLTE_U_SPECIAL_4_OPCODE_Y1 = 1,
SLTH_SPECIAL_0_OPCODE_X0 = 81,
SLTH_SPECIAL_0_OPCODE_X1 = 51,
SLTH_U_SPECIAL_0_OPCODE_X0 = 82,
SLTH_U_SPECIAL_0_OPCODE_X1 = 52,
SLTIB_IMM_0_OPCODE_X0 = 12,
SLTIB_IMM_0_OPCODE_X1 = 15,
SLTIB_U_IMM_0_OPCODE_X0 = 13,
SLTIB_U_IMM_0_OPCODE_X1 = 16,
SLTIH_IMM_0_OPCODE_X0 = 14,
SLTIH_IMM_0_OPCODE_X1 = 17,
SLTIH_U_IMM_0_OPCODE_X0 = 15,
SLTIH_U_IMM_0_OPCODE_X1 = 18,
SLTI_IMM_0_OPCODE_X0 = 16,
SLTI_IMM_0_OPCODE_X1 = 19,
SLTI_OPCODE_Y0 = 14,
SLTI_OPCODE_Y1 = 12,
SLTI_U_IMM_0_OPCODE_X0 = 17,
SLTI_U_IMM_0_OPCODE_X1 = 20,
SLTI_U_OPCODE_Y0 = 15,
SLTI_U_OPCODE_Y1 = 13,
SLT_SPECIAL_0_OPCODE_X0 = 83,
SLT_SPECIAL_0_OPCODE_X1 = 53,
SLT_SPECIAL_4_OPCODE_Y0 = 2,
SLT_SPECIAL_4_OPCODE_Y1 = 2,
SLT_U_SPECIAL_0_OPCODE_X0 = 84,
SLT_U_SPECIAL_0_OPCODE_X1 = 54,
SLT_U_SPECIAL_4_OPCODE_Y0 = 3,
SLT_U_SPECIAL_4_OPCODE_Y1 = 3,
SNEB_SPECIAL_0_OPCODE_X0 = 85,
SNEB_SPECIAL_0_OPCODE_X1 = 55,
SNEH_SPECIAL_0_OPCODE_X0 = 86,
SNEH_SPECIAL_0_OPCODE_X1 = 56,
SNE_SPECIAL_0_OPCODE_X0 = 87,
SNE_SPECIAL_0_OPCODE_X1 = 57,
SNE_SPECIAL_5_OPCODE_Y0 = 3,
SNE_SPECIAL_5_OPCODE_Y1 = 3,
SPECIAL_0_OPCODE_X0 = 0,
SPECIAL_0_OPCODE_X1 = 1,
SPECIAL_0_OPCODE_Y0 = 1,
SPECIAL_0_OPCODE_Y1 = 1,
SPECIAL_1_OPCODE_Y0 = 2,
SPECIAL_1_OPCODE_Y1 = 2,
SPECIAL_2_OPCODE_Y0 = 3,
SPECIAL_2_OPCODE_Y1 = 3,
SPECIAL_3_OPCODE_Y0 = 4,
SPECIAL_3_OPCODE_Y1 = 4,
SPECIAL_4_OPCODE_Y0 = 5,
SPECIAL_4_OPCODE_Y1 = 5,
SPECIAL_5_OPCODE_Y0 = 6,
SPECIAL_5_OPCODE_Y1 = 6,
SPECIAL_6_OPCODE_Y0 = 7,
SPECIAL_7_OPCODE_Y0 = 8,
SRAB_SPECIAL_0_OPCODE_X0 = 88,
SRAB_SPECIAL_0_OPCODE_X1 = 58,
SRAH_SPECIAL_0_OPCODE_X0 = 89,
SRAH_SPECIAL_0_OPCODE_X1 = 59,
SRAIB_SHUN_0_OPCODE_X0 = 8,
SRAIB_SHUN_0_OPCODE_X1 = 8,
SRAIH_SHUN_0_OPCODE_X0 = 9,
SRAIH_SHUN_0_OPCODE_X1 = 9,
SRAI_SHUN_0_OPCODE_X0 = 10,
SRAI_SHUN_0_OPCODE_X1 = 10,
SRAI_SHUN_0_OPCODE_Y0 = 4,
SRAI_SHUN_0_OPCODE_Y1 = 4,
SRA_SPECIAL_0_OPCODE_X0 = 90,
SRA_SPECIAL_0_OPCODE_X1 = 60,
SRA_SPECIAL_3_OPCODE_Y0 = 3,
SRA_SPECIAL_3_OPCODE_Y1 = 3,
SUBBS_U_SPECIAL_0_OPCODE_X0 = 100,
SUBBS_U_SPECIAL_0_OPCODE_X1 = 70,
SUBB_SPECIAL_0_OPCODE_X0 = 91,
SUBB_SPECIAL_0_OPCODE_X1 = 61,
SUBHS_SPECIAL_0_OPCODE_X0 = 101,
SUBHS_SPECIAL_0_OPCODE_X1 = 71,
SUBH_SPECIAL_0_OPCODE_X0 = 92,
SUBH_SPECIAL_0_OPCODE_X1 = 62,
SUBS_SPECIAL_0_OPCODE_X0 = 97,
SUBS_SPECIAL_0_OPCODE_X1 = 67,
SUB_SPECIAL_0_OPCODE_X0 = 93,
SUB_SPECIAL_0_OPCODE_X1 = 63,
SUB_SPECIAL_0_OPCODE_Y0 = 3,
SUB_SPECIAL_0_OPCODE_Y1 = 3,
SWADD_IMM_0_OPCODE_X1 = 30,
SWINT0_UN_0_SHUN_0_OPCODE_X1 = 18,
SWINT1_UN_0_SHUN_0_OPCODE_X1 = 19,
SWINT2_UN_0_SHUN_0_OPCODE_X1 = 20,
SWINT3_UN_0_SHUN_0_OPCODE_X1 = 21,
SW_OPCODE_Y2 = 7,
SW_SPECIAL_0_OPCODE_X1 = 64,
TBLIDXB0_UN_0_SHUN_0_OPCODE_X0 = 8,
TBLIDXB0_UN_0_SHUN_0_OPCODE_Y0 = 8,
TBLIDXB1_UN_0_SHUN_0_OPCODE_X0 = 9,
TBLIDXB1_UN_0_SHUN_0_OPCODE_Y0 = 9,
TBLIDXB2_UN_0_SHUN_0_OPCODE_X0 = 10,
TBLIDXB2_UN_0_SHUN_0_OPCODE_Y0 = 10,
TBLIDXB3_UN_0_SHUN_0_OPCODE_X0 = 11,
TBLIDXB3_UN_0_SHUN_0_OPCODE_Y0 = 11,
TNS_UN_0_SHUN_0_OPCODE_X1 = 22,
UN_0_SHUN_0_OPCODE_X0 = 11,
UN_0_SHUN_0_OPCODE_X1 = 11,
UN_0_SHUN_0_OPCODE_Y0 = 5,
UN_0_SHUN_0_OPCODE_Y1 = 5,
WH64_UN_0_SHUN_0_OPCODE_X1 = 23,
XORI_IMM_0_OPCODE_X0 = 2,
XORI_IMM_0_OPCODE_X1 = 21,
XOR_SPECIAL_0_OPCODE_X0 = 94,
XOR_SPECIAL_0_OPCODE_X1 = 65,
XOR_SPECIAL_2_OPCODE_Y0 = 3,
XOR_SPECIAL_2_OPCODE_Y1 = 3
};
#endif /* !_TILE_OPCODE_CONSTANTS_H */

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arch/tile/include/asm/opcode_constants_64.h
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@ -1,609 +0,0 @@
/*
* Copyright 2011 Tilera Corporation. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation, version 2.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
* NON INFRINGEMENT. See the GNU General Public License for
* more details.
*/
/* This file is machine-generated; DO NOT EDIT! */
#ifndef _TILE_OPCODE_CONSTANTS_H
#define _TILE_OPCODE_CONSTANTS_H
enum
{
ADDI_IMM8_OPCODE_X0 = 1,
ADDI_IMM8_OPCODE_X1 = 1,
ADDI_OPCODE_Y0 = 0,
ADDI_OPCODE_Y1 = 1,
ADDLI_OPCODE_X0 = 1,
ADDLI_OPCODE_X1 = 0,
ADDXI_IMM8_OPCODE_X0 = 2,
ADDXI_IMM8_OPCODE_X1 = 2,
ADDXI_OPCODE_Y0 = 1,
ADDXI_OPCODE_Y1 = 2,
ADDXLI_OPCODE_X0 = 2,
ADDXLI_OPCODE_X1 = 1,
ADDXSC_RRR_0_OPCODE_X0 = 1,
ADDXSC_RRR_0_OPCODE_X1 = 1,
ADDX_RRR_0_OPCODE_X0 = 2,
ADDX_RRR_0_OPCODE_X1 = 2,
ADDX_RRR_0_OPCODE_Y0 = 0,
ADDX_SPECIAL_0_OPCODE_Y1 = 0,
ADD_RRR_0_OPCODE_X0 = 3,
ADD_RRR_0_OPCODE_X1 = 3,
ADD_RRR_0_OPCODE_Y0 = 1,
ADD_SPECIAL_0_OPCODE_Y1 = 1,
ANDI_IMM8_OPCODE_X0 = 3,
ANDI_IMM8_OPCODE_X1 = 3,
ANDI_OPCODE_Y0 = 2,
ANDI_OPCODE_Y1 = 3,
AND_RRR_0_OPCODE_X0 = 4,
AND_RRR_0_OPCODE_X1 = 4,
AND_RRR_5_OPCODE_Y0 = 0,
AND_RRR_5_OPCODE_Y1 = 0,
BEQZT_BRANCH_OPCODE_X1 = 16,
BEQZ_BRANCH_OPCODE_X1 = 17,
BFEXTS_BF_OPCODE_X0 = 4,
BFEXTU_BF_OPCODE_X0 = 5,
BFINS_BF_OPCODE_X0 = 6,
BF_OPCODE_X0 = 3,
BGEZT_BRANCH_OPCODE_X1 = 18,
BGEZ_BRANCH_OPCODE_X1 = 19,
BGTZT_BRANCH_OPCODE_X1 = 20,
BGTZ_BRANCH_OPCODE_X1 = 21,
BLBCT_BRANCH_OPCODE_X1 = 22,
BLBC_BRANCH_OPCODE_X1 = 23,
BLBST_BRANCH_OPCODE_X1 = 24,
BLBS_BRANCH_OPCODE_X1 = 25,
BLEZT_BRANCH_OPCODE_X1 = 26,
BLEZ_BRANCH_OPCODE_X1 = 27,
BLTZT_BRANCH_OPCODE_X1 = 28,
BLTZ_BRANCH_OPCODE_X1 = 29,
BNEZT_BRANCH_OPCODE_X1 = 30,
BNEZ_BRANCH_OPCODE_X1 = 31,
BRANCH_OPCODE_X1 = 2,
CMOVEQZ_RRR_0_OPCODE_X0 = 5,
CMOVEQZ_RRR_4_OPCODE_Y0 = 0,
CMOVNEZ_RRR_0_OPCODE_X0 = 6,
CMOVNEZ_RRR_4_OPCODE_Y0 = 1,
CMPEQI_IMM8_OPCODE_X0 = 4,
CMPEQI_IMM8_OPCODE_X1 = 4,
CMPEQI_OPCODE_Y0 = 3,
CMPEQI_OPCODE_Y1 = 4,
CMPEQ_RRR_0_OPCODE_X0 = 7,
CMPEQ_RRR_0_OPCODE_X1 = 5,
CMPEQ_RRR_3_OPCODE_Y0 = 0,
CMPEQ_RRR_3_OPCODE_Y1 = 2,
CMPEXCH4_RRR_0_OPCODE_X1 = 6,
CMPEXCH_RRR_0_OPCODE_X1 = 7,
CMPLES_RRR_0_OPCODE_X0 = 8,
CMPLES_RRR_0_OPCODE_X1 = 8,
CMPLES_RRR_2_OPCODE_Y0 = 0,
CMPLES_RRR_2_OPCODE_Y1 = 0,
CMPLEU_RRR_0_OPCODE_X0 = 9,
CMPLEU_RRR_0_OPCODE_X1 = 9,
CMPLEU_RRR_2_OPCODE_Y0 = 1,
CMPLEU_RRR_2_OPCODE_Y1 = 1,
CMPLTSI_IMM8_OPCODE_X0 = 5,
CMPLTSI_IMM8_OPCODE_X1 = 5,
CMPLTSI_OPCODE_Y0 = 4,
CMPLTSI_OPCODE_Y1 = 5,
CMPLTS_RRR_0_OPCODE_X0 = 10,
CMPLTS_RRR_0_OPCODE_X1 = 10,
CMPLTS_RRR_2_OPCODE_Y0 = 2,
CMPLTS_RRR_2_OPCODE_Y1 = 2,
CMPLTUI_IMM8_OPCODE_X0 = 6,
CMPLTUI_IMM8_OPCODE_X1 = 6,
CMPLTU_RRR_0_OPCODE_X0 = 11,
CMPLTU_RRR_0_OPCODE_X1 = 11,
CMPLTU_RRR_2_OPCODE_Y0 = 3,
CMPLTU_RRR_2_OPCODE_Y1 = 3,
CMPNE_RRR_0_OPCODE_X0 = 12,
CMPNE_RRR_0_OPCODE_X1 = 12,
CMPNE_RRR_3_OPCODE_Y0 = 1,
CMPNE_RRR_3_OPCODE_Y1 = 3,
CMULAF_RRR_0_OPCODE_X0 = 13,
CMULA_RRR_0_OPCODE_X0 = 14,
CMULFR_RRR_0_OPCODE_X0 = 15,
CMULF_RRR_0_OPCODE_X0 = 16,
CMULHR_RRR_0_OPCODE_X0 = 17,
CMULH_RRR_0_OPCODE_X0 = 18,
CMUL_RRR_0_OPCODE_X0 = 19,
CNTLZ_UNARY_OPCODE_X0 = 1,
CNTLZ_UNARY_OPCODE_Y0 = 1,
CNTTZ_UNARY_OPCODE_X0 = 2,
CNTTZ_UNARY_OPCODE_Y0 = 2,
CRC32_32_RRR_0_OPCODE_X0 = 20,
CRC32_8_RRR_0_OPCODE_X0 = 21,
DBLALIGN2_RRR_0_OPCODE_X0 = 22,
DBLALIGN2_RRR_0_OPCODE_X1 = 13,
DBLALIGN4_RRR_0_OPCODE_X0 = 23,
DBLALIGN4_RRR_0_OPCODE_X1 = 14,
DBLALIGN6_RRR_0_OPCODE_X0 = 24,
DBLALIGN6_RRR_0_OPCODE_X1 = 15,
DBLALIGN_RRR_0_OPCODE_X0 = 25,
DRAIN_UNARY_OPCODE_X1 = 1,
DTLBPR_UNARY_OPCODE_X1 = 2,
EXCH4_RRR_0_OPCODE_X1 = 16,
EXCH_RRR_0_OPCODE_X1 = 17,
FDOUBLE_ADDSUB_RRR_0_OPCODE_X0 = 26,
FDOUBLE_ADD_FLAGS_RRR_0_OPCODE_X0 = 27,
FDOUBLE_MUL_FLAGS_RRR_0_OPCODE_X0 = 28,
FDOUBLE_PACK1_RRR_0_OPCODE_X0 = 29,
FDOUBLE_PACK2_RRR_0_OPCODE_X0 = 30,
FDOUBLE_SUB_FLAGS_RRR_0_OPCODE_X0 = 31,
FDOUBLE_UNPACK_MAX_RRR_0_OPCODE_X0 = 32,
FDOUBLE_UNPACK_MIN_RRR_0_OPCODE_X0 = 33,
FETCHADD4_RRR_0_OPCODE_X1 = 18,
FETCHADDGEZ4_RRR_0_OPCODE_X1 = 19,
FETCHADDGEZ_RRR_0_OPCODE_X1 = 20,
FETCHADD_RRR_0_OPCODE_X1 = 21,
FETCHAND4_RRR_0_OPCODE_X1 = 22,
FETCHAND_RRR_0_OPCODE_X1 = 23,
FETCHOR4_RRR_0_OPCODE_X1 = 24,
FETCHOR_RRR_0_OPCODE_X1 = 25,
FINV_UNARY_OPCODE_X1 = 3,
FLUSHWB_UNARY_OPCODE_X1 = 4,
FLUSH_UNARY_OPCODE_X1 = 5,
FNOP_UNARY_OPCODE_X0 = 3,
FNOP_UNARY_OPCODE_X1 = 6,
FNOP_UNARY_OPCODE_Y0 = 3,
FNOP_UNARY_OPCODE_Y1 = 8,
FSINGLE_ADD1_RRR_0_OPCODE_X0 = 34,
FSINGLE_ADDSUB2_RRR_0_OPCODE_X0 = 35,
FSINGLE_MUL1_RRR_0_OPCODE_X0 = 36,
FSINGLE_MUL2_RRR_0_OPCODE_X0 = 37,
FSINGLE_PACK1_UNARY_OPCODE_X0 = 4,
FSINGLE_PACK1_UNARY_OPCODE_Y0 = 4,
FSINGLE_PACK2_RRR_0_OPCODE_X0 = 38,
FSINGLE_SUB1_RRR_0_OPCODE_X0 = 39,
ICOH_UNARY_OPCODE_X1 = 7,
ILL_UNARY_OPCODE_X1 = 8,
ILL_UNARY_OPCODE_Y1 = 9,
IMM8_OPCODE_X0 = 4,
IMM8_OPCODE_X1 = 3,
INV_UNARY_OPCODE_X1 = 9,
IRET_UNARY_OPCODE_X1 = 10,
JALRP_UNARY_OPCODE_X1 = 11,
JALRP_UNARY_OPCODE_Y1 = 10,
JALR_UNARY_OPCODE_X1 = 12,
JALR_UNARY_OPCODE_Y1 = 11,
JAL_JUMP_OPCODE_X1 = 0,
JRP_UNARY_OPCODE_X1 = 13,
JRP_UNARY_OPCODE_Y1 = 12,
JR_UNARY_OPCODE_X1 = 14,
JR_UNARY_OPCODE_Y1 = 13,
JUMP_OPCODE_X1 = 4,
J_JUMP_OPCODE_X1 = 1,
LD1S_ADD_IMM8_OPCODE_X1 = 7,
LD1S_OPCODE_Y2 = 0,
LD1S_UNARY_OPCODE_X1 = 15,
LD1U_ADD_IMM8_OPCODE_X1 = 8,
LD1U_OPCODE_Y2 = 1,
LD1U_UNARY_OPCODE_X1 = 16,
LD2S_ADD_IMM8_OPCODE_X1 = 9,
LD2S_OPCODE_Y2 = 2,
LD2S_UNARY_OPCODE_X1 = 17,
LD2U_ADD_IMM8_OPCODE_X1 = 10,
LD2U_OPCODE_Y2 = 3,
LD2U_UNARY_OPCODE_X1 = 18,
LD4S_ADD_IMM8_OPCODE_X1 = 11,
LD4S_OPCODE_Y2 = 1,
LD4S_UNARY_OPCODE_X1 = 19,
LD4U_ADD_IMM8_OPCODE_X1 = 12,
LD4U_OPCODE_Y2 = 2,
LD4U_UNARY_OPCODE_X1 = 20,
LDNA_UNARY_OPCODE_X1 = 21,
LDNT1S_ADD_IMM8_OPCODE_X1 = 13,
LDNT1S_UNARY_OPCODE_X1 = 22,
LDNT1U_ADD_IMM8_OPCODE_X1 = 14,
LDNT1U_UNARY_OPCODE_X1 = 23,
LDNT2S_ADD_IMM8_OPCODE_X1 = 15,
LDNT2S_UNARY_OPCODE_X1 = 24,
LDNT2U_ADD_IMM8_OPCODE_X1 = 16,
LDNT2U_UNARY_OPCODE_X1 = 25,
LDNT4S_ADD_IMM8_OPCODE_X1 = 17,
LDNT4S_UNARY_OPCODE_X1 = 26,
LDNT4U_ADD_IMM8_OPCODE_X1 = 18,
LDNT4U_UNARY_OPCODE_X1 = 27,
LDNT_ADD_IMM8_OPCODE_X1 = 19,
LDNT_UNARY_OPCODE_X1 = 28,
LD_ADD_IMM8_OPCODE_X1 = 20,
LD_OPCODE_Y2 = 3,
LD_UNARY_OPCODE_X1 = 29,
LNK_UNARY_OPCODE_X1 = 30,
LNK_UNARY_OPCODE_Y1 = 14,
LWNA_ADD_IMM8_OPCODE_X1 = 21,
MFSPR_IMM8_OPCODE_X1 = 22,
MF_UNARY_OPCODE_X1 = 31,
MM_BF_OPCODE_X0 = 7,
MNZ_RRR_0_OPCODE_X0 = 40,
MNZ_RRR_0_OPCODE_X1 = 26,
MNZ_RRR_4_OPCODE_Y0 = 2,
MNZ_RRR_4_OPCODE_Y1 = 2,
MODE_OPCODE_YA2 = 1,
MODE_OPCODE_YB2 = 2,
MODE_OPCODE_YC2 = 3,
MTSPR_IMM8_OPCODE_X1 = 23,
MULAX_RRR_0_OPCODE_X0 = 41,
MULAX_RRR_3_OPCODE_Y0 = 2,
MULA_HS_HS_RRR_0_OPCODE_X0 = 42,
MULA_HS_HS_RRR_9_OPCODE_Y0 = 0,
MULA_HS_HU_RRR_0_OPCODE_X0 = 43,
MULA_HS_LS_RRR_0_OPCODE_X0 = 44,
MULA_HS_LU_RRR_0_OPCODE_X0 = 45,
MULA_HU_HU_RRR_0_OPCODE_X0 = 46,
MULA_HU_HU_RRR_9_OPCODE_Y0 = 1,
MULA_HU_LS_RRR_0_OPCODE_X0 = 47,
MULA_HU_LU_RRR_0_OPCODE_X0 = 48,
MULA_LS_LS_RRR_0_OPCODE_X0 = 49,
MULA_LS_LS_RRR_9_OPCODE_Y0 = 2,
MULA_LS_LU_RRR_0_OPCODE_X0 = 50,
MULA_LU_LU_RRR_0_OPCODE_X0 = 51,
MULA_LU_LU_RRR_9_OPCODE_Y0 = 3,
MULX_RRR_0_OPCODE_X0 = 52,
MULX_RRR_3_OPCODE_Y0 = 3,
MUL_HS_HS_RRR_0_OPCODE_X0 = 53,
MUL_HS_HS_RRR_8_OPCODE_Y0 = 0,
MUL_HS_HU_RRR_0_OPCODE_X0 = 54,
MUL_HS_LS_RRR_0_OPCODE_X0 = 55,
MUL_HS_LU_RRR_0_OPCODE_X0 = 56,
MUL_HU_HU_RRR_0_OPCODE_X0 = 57,
MUL_HU_HU_RRR_8_OPCODE_Y0 = 1,
MUL_HU_LS_RRR_0_OPCODE_X0 = 58,
MUL_HU_LU_RRR_0_OPCODE_X0 = 59,
MUL_LS_LS_RRR_0_OPCODE_X0 = 60,
MUL_LS_LS_RRR_8_OPCODE_Y0 = 2,
MUL_LS_LU_RRR_0_OPCODE_X0 = 61,
MUL_LU_LU_RRR_0_OPCODE_X0 = 62,
MUL_LU_LU_RRR_8_OPCODE_Y0 = 3,
MZ_RRR_0_OPCODE_X0 = 63,
MZ_RRR_0_OPCODE_X1 = 27,
MZ_RRR_4_OPCODE_Y0 = 3,
MZ_RRR_4_OPCODE_Y1 = 3,
NAP_UNARY_OPCODE_X1 = 32,
NOP_UNARY_OPCODE_X0 = 5,
NOP_UNARY_OPCODE_X1 = 33,
NOP_UNARY_OPCODE_Y0 = 5,
NOP_UNARY_OPCODE_Y1 = 15,
NOR_RRR_0_OPCODE_X0 = 64,
NOR_RRR_0_OPCODE_X1 = 28,
NOR_RRR_5_OPCODE_Y0 = 1,
NOR_RRR_5_OPCODE_Y1 = 1,
ORI_IMM8_OPCODE_X0 = 7,
ORI_IMM8_OPCODE_X1 = 24,
OR_RRR_0_OPCODE_X0 = 65,
OR_RRR_0_OPCODE_X1 = 29,
OR_RRR_5_OPCODE_Y0 = 2,
OR_RRR_5_OPCODE_Y1 = 2,
PCNT_UNARY_OPCODE_X0 = 6,
PCNT_UNARY_OPCODE_Y0 = 6,
REVBITS_UNARY_OPCODE_X0 = 7,
REVBITS_UNARY_OPCODE_Y0 = 7,
REVBYTES_UNARY_OPCODE_X0 = 8,
REVBYTES_UNARY_OPCODE_Y0 = 8,
ROTLI_SHIFT_OPCODE_X0 = 1,
ROTLI_SHIFT_OPCODE_X1 = 1,
ROTLI_SHIFT_OPCODE_Y0 = 0,
ROTLI_SHIFT_OPCODE_Y1 = 0,
ROTL_RRR_0_OPCODE_X0 = 66,
ROTL_RRR_0_OPCODE_X1 = 30,
ROTL_RRR_6_OPCODE_Y0 = 0,
ROTL_RRR_6_OPCODE_Y1 = 0,
RRR_0_OPCODE_X0 = 5,
RRR_0_OPCODE_X1 = 5,
RRR_0_OPCODE_Y0 = 5,
RRR_0_OPCODE_Y1 = 6,
RRR_1_OPCODE_Y0 = 6,
RRR_1_OPCODE_Y1 = 7,
RRR_2_OPCODE_Y0 = 7,
RRR_2_OPCODE_Y1 = 8,
RRR_3_OPCODE_Y0 = 8,
RRR_3_OPCODE_Y1 = 9,
RRR_4_OPCODE_Y0 = 9,
RRR_4_OPCODE_Y1 = 10,
RRR_5_OPCODE_Y0 = 10,
RRR_5_OPCODE_Y1 = 11,
RRR_6_OPCODE_Y0 = 11,
RRR_6_OPCODE_Y1 = 12,
RRR_7_OPCODE_Y0 = 12,
RRR_7_OPCODE_Y1 = 13,
RRR_8_OPCODE_Y0 = 13,
RRR_9_OPCODE_Y0 = 14,
SHIFT_OPCODE_X0 = 6,
SHIFT_OPCODE_X1 = 6,
SHIFT_OPCODE_Y0 = 15,
SHIFT_OPCODE_Y1 = 14,
SHL16INSLI_OPCODE_X0 = 7,
SHL16INSLI_OPCODE_X1 = 7,
SHL1ADDX_RRR_0_OPCODE_X0 = 67,
SHL1ADDX_RRR_0_OPCODE_X1 = 31,
SHL1ADDX_RRR_7_OPCODE_Y0 = 1,
SHL1ADDX_RRR_7_OPCODE_Y1 = 1,
SHL1ADD_RRR_0_OPCODE_X0 = 68,
SHL1ADD_RRR_0_OPCODE_X1 = 32,
SHL1ADD_RRR_1_OPCODE_Y0 = 0,
SHL1ADD_RRR_1_OPCODE_Y1 = 0,
SHL2ADDX_RRR_0_OPCODE_X0 = 69,
SHL2ADDX_RRR_0_OPCODE_X1 = 33,
SHL2ADDX_RRR_7_OPCODE_Y0 = 2,
SHL2ADDX_RRR_7_OPCODE_Y1 = 2,
SHL2ADD_RRR_0_OPCODE_X0 = 70,
SHL2ADD_RRR_0_OPCODE_X1 = 34,
SHL2ADD_RRR_1_OPCODE_Y0 = 1,
SHL2ADD_RRR_1_OPCODE_Y1 = 1,
SHL3ADDX_RRR_0_OPCODE_X0 = 71,
SHL3ADDX_RRR_0_OPCODE_X1 = 35,
SHL3ADDX_RRR_7_OPCODE_Y0 = 3,
SHL3ADDX_RRR_7_OPCODE_Y1 = 3,
SHL3ADD_RRR_0_OPCODE_X0 = 72,
SHL3ADD_RRR_0_OPCODE_X1 = 36,
SHL3ADD_RRR_1_OPCODE_Y0 = 2,
SHL3ADD_RRR_1_OPCODE_Y1 = 2,
SHLI_SHIFT_OPCODE_X0 = 2,
SHLI_SHIFT_OPCODE_X1 = 2,
SHLI_SHIFT_OPCODE_Y0 = 1,
SHLI_SHIFT_OPCODE_Y1 = 1,
SHLXI_SHIFT_OPCODE_X0 = 3,
SHLXI_SHIFT_OPCODE_X1 = 3,
SHLX_RRR_0_OPCODE_X0 = 73,
SHLX_RRR_0_OPCODE_X1 = 37,
SHL_RRR_0_OPCODE_X0 = 74,
SHL_RRR_0_OPCODE_X1 = 38,
SHL_RRR_6_OPCODE_Y0 = 1,
SHL_RRR_6_OPCODE_Y1 = 1,
SHRSI_SHIFT_OPCODE_X0 = 4,
SHRSI_SHIFT_OPCODE_X1 = 4,
SHRSI_SHIFT_OPCODE_Y0 = 2,
SHRSI_SHIFT_OPCODE_Y1 = 2,
SHRS_RRR_0_OPCODE_X0 = 75,
SHRS_RRR_0_OPCODE_X1 = 39,
SHRS_RRR_6_OPCODE_Y0 = 2,
SHRS_RRR_6_OPCODE_Y1 = 2,
SHRUI_SHIFT_OPCODE_X0 = 5,
SHRUI_SHIFT_OPCODE_X1 = 5,
SHRUI_SHIFT_OPCODE_Y0 = 3,
SHRUI_SHIFT_OPCODE_Y1 = 3,
SHRUXI_SHIFT_OPCODE_X0 = 6,
SHRUXI_SHIFT_OPCODE_X1 = 6,
SHRUX_RRR_0_OPCODE_X0 = 76,
SHRUX_RRR_0_OPCODE_X1 = 40,
SHRU_RRR_0_OPCODE_X0 = 77,
SHRU_RRR_0_OPCODE_X1 = 41,
SHRU_RRR_6_OPCODE_Y0 = 3,
SHRU_RRR_6_OPCODE_Y1 = 3,
SHUFFLEBYTES_RRR_0_OPCODE_X0 = 78,
ST1_ADD_IMM8_OPCODE_X1 = 25,
ST1_OPCODE_Y2 = 0,
ST1_RRR_0_OPCODE_X1 = 42,
ST2_ADD_IMM8_OPCODE_X1 = 26,
ST2_OPCODE_Y2 = 1,
ST2_RRR_0_OPCODE_X1 = 43,
ST4_ADD_IMM8_OPCODE_X1 = 27,
ST4_OPCODE_Y2 = 2,
ST4_RRR_0_OPCODE_X1 = 44,
STNT1_ADD_IMM8_OPCODE_X1 = 28,
STNT1_RRR_0_OPCODE_X1 = 45,
STNT2_ADD_IMM8_OPCODE_X1 = 29,
STNT2_RRR_0_OPCODE_X1 = 46,
STNT4_ADD_IMM8_OPCODE_X1 = 30,
STNT4_RRR_0_OPCODE_X1 = 47,
STNT_ADD_IMM8_OPCODE_X1 = 31,
STNT_RRR_0_OPCODE_X1 = 48,
ST_ADD_IMM8_OPCODE_X1 = 32,
ST_OPCODE_Y2 = 3,
ST_RRR_0_OPCODE_X1 = 49,
SUBXSC_RRR_0_OPCODE_X0 = 79,
SUBXSC_RRR_0_OPCODE_X1 = 50,
SUBX_RRR_0_OPCODE_X0 = 80,
SUBX_RRR_0_OPCODE_X1 = 51,
SUBX_RRR_0_OPCODE_Y0 = 2,
SUBX_RRR_0_OPCODE_Y1 = 2,
SUB_RRR_0_OPCODE_X0 = 81,
SUB_RRR_0_OPCODE_X1 = 52,
SUB_RRR_0_OPCODE_Y0 = 3,
SUB_RRR_0_OPCODE_Y1 = 3,
SWINT0_UNARY_OPCODE_X1 = 34,
SWINT1_UNARY_OPCODE_X1 = 35,
SWINT2_UNARY_OPCODE_X1 = 36,
SWINT3_UNARY_OPCODE_X1 = 37,
TBLIDXB0_UNARY_OPCODE_X0 = 9,
TBLIDXB0_UNARY_OPCODE_Y0 = 9,
TBLIDXB1_UNARY_OPCODE_X0 = 10,
TBLIDXB1_UNARY_OPCODE_Y0 = 10,
TBLIDXB2_UNARY_OPCODE_X0 = 11,
TBLIDXB2_UNARY_OPCODE_Y0 = 11,
TBLIDXB3_UNARY_OPCODE_X0 = 12,
TBLIDXB3_UNARY_OPCODE_Y0 = 12,
UNARY_RRR_0_OPCODE_X0 = 82,
UNARY_RRR_0_OPCODE_X1 = 53,
UNARY_RRR_1_OPCODE_Y0 = 3,
UNARY_RRR_1_OPCODE_Y1 = 3,
V1ADDI_IMM8_OPCODE_X0 = 8,
V1ADDI_IMM8_OPCODE_X1 = 33,
V1ADDUC_RRR_0_OPCODE_X0 = 83,
V1ADDUC_RRR_0_OPCODE_X1 = 54,
V1ADD_RRR_0_OPCODE_X0 = 84,
V1ADD_RRR_0_OPCODE_X1 = 55,
V1ADIFFU_RRR_0_OPCODE_X0 = 85,
V1AVGU_RRR_0_OPCODE_X0 = 86,
V1CMPEQI_IMM8_OPCODE_X0 = 9,
V1CMPEQI_IMM8_OPCODE_X1 = 34,
V1CMPEQ_RRR_0_OPCODE_X0 = 87,
V1CMPEQ_RRR_0_OPCODE_X1 = 56,
V1CMPLES_RRR_0_OPCODE_X0 = 88,
V1CMPLES_RRR_0_OPCODE_X1 = 57,
V1CMPLEU_RRR_0_OPCODE_X0 = 89,
V1CMPLEU_RRR_0_OPCODE_X1 = 58,
V1CMPLTSI_IMM8_OPCODE_X0 = 10,
V1CMPLTSI_IMM8_OPCODE_X1 = 35,
V1CMPLTS_RRR_0_OPCODE_X0 = 90,
V1CMPLTS_RRR_0_OPCODE_X1 = 59,
V1CMPLTUI_IMM8_OPCODE_X0 = 11,
V1CMPLTUI_IMM8_OPCODE_X1 = 36,
V1CMPLTU_RRR_0_OPCODE_X0 = 91,
V1CMPLTU_RRR_0_OPCODE_X1 = 60,
V1CMPNE_RRR_0_OPCODE_X0 = 92,
V1CMPNE_RRR_0_OPCODE_X1 = 61,
V1DDOTPUA_RRR_0_OPCODE_X0 = 161,
V1DDOTPUSA_RRR_0_OPCODE_X0 = 93,
V1DDOTPUS_RRR_0_OPCODE_X0 = 94,
V1DDOTPU_RRR_0_OPCODE_X0 = 162,
V1DOTPA_RRR_0_OPCODE_X0 = 95,
V1DOTPUA_RRR_0_OPCODE_X0 = 163,
V1DOTPUSA_RRR_0_OPCODE_X0 = 96,
V1DOTPUS_RRR_0_OPCODE_X0 = 97,
V1DOTPU_RRR_0_OPCODE_X0 = 164,
V1DOTP_RRR_0_OPCODE_X0 = 98,
V1INT_H_RRR_0_OPCODE_X0 = 99,
V1INT_H_RRR_0_OPCODE_X1 = 62,
V1INT_L_RRR_0_OPCODE_X0 = 100,
V1INT_L_RRR_0_OPCODE_X1 = 63,
V1MAXUI_IMM8_OPCODE_X0 = 12,
V1MAXUI_IMM8_OPCODE_X1 = 37,
V1MAXU_RRR_0_OPCODE_X0 = 101,
V1MAXU_RRR_0_OPCODE_X1 = 64,
V1MINUI_IMM8_OPCODE_X0 = 13,
V1MINUI_IMM8_OPCODE_X1 = 38,
V1MINU_RRR_0_OPCODE_X0 = 102,
V1MINU_RRR_0_OPCODE_X1 = 65,
V1MNZ_RRR_0_OPCODE_X0 = 103,
V1MNZ_RRR_0_OPCODE_X1 = 66,
V1MULTU_RRR_0_OPCODE_X0 = 104,
V1MULUS_RRR_0_OPCODE_X0 = 105,
V1MULU_RRR_0_OPCODE_X0 = 106,
V1MZ_RRR_0_OPCODE_X0 = 107,
V1MZ_RRR_0_OPCODE_X1 = 67,
V1SADAU_RRR_0_OPCODE_X0 = 108,
V1SADU_RRR_0_OPCODE_X0 = 109,
V1SHLI_SHIFT_OPCODE_X0 = 7,
V1SHLI_SHIFT_OPCODE_X1 = 7,
V1SHL_RRR_0_OPCODE_X0 = 110,
V1SHL_RRR_0_OPCODE_X1 = 68,
V1SHRSI_SHIFT_OPCODE_X0 = 8,
V1SHRSI_SHIFT_OPCODE_X1 = 8,
V1SHRS_RRR_0_OPCODE_X0 = 111,
V1SHRS_RRR_0_OPCODE_X1 = 69,
V1SHRUI_SHIFT_OPCODE_X0 = 9,
V1SHRUI_SHIFT_OPCODE_X1 = 9,
V1SHRU_RRR_0_OPCODE_X0 = 112,
V1SHRU_RRR_0_OPCODE_X1 = 70,
V1SUBUC_RRR_0_OPCODE_X0 = 113,
V1SUBUC_RRR_0_OPCODE_X1 = 71,
V1SUB_RRR_0_OPCODE_X0 = 114,
V1SUB_RRR_0_OPCODE_X1 = 72,
V2ADDI_IMM8_OPCODE_X0 = 14,
V2ADDI_IMM8_OPCODE_X1 = 39,
V2ADDSC_RRR_0_OPCODE_X0 = 115,
V2ADDSC_RRR_0_OPCODE_X1 = 73,
V2ADD_RRR_0_OPCODE_X0 = 116,
V2ADD_RRR_0_OPCODE_X1 = 74,
V2ADIFFS_RRR_0_OPCODE_X0 = 117,
V2AVGS_RRR_0_OPCODE_X0 = 118,
V2CMPEQI_IMM8_OPCODE_X0 = 15,
V2CMPEQI_IMM8_OPCODE_X1 = 40,
V2CMPEQ_RRR_0_OPCODE_X0 = 119,
V2CMPEQ_RRR_0_OPCODE_X1 = 75,
V2CMPLES_RRR_0_OPCODE_X0 = 120,
V2CMPLES_RRR_0_OPCODE_X1 = 76,
V2CMPLEU_RRR_0_OPCODE_X0 = 121,
V2CMPLEU_RRR_0_OPCODE_X1 = 77,
V2CMPLTSI_IMM8_OPCODE_X0 = 16,
V2CMPLTSI_IMM8_OPCODE_X1 = 41,
V2CMPLTS_RRR_0_OPCODE_X0 = 122,
V2CMPLTS_RRR_0_OPCODE_X1 = 78,
V2CMPLTUI_IMM8_OPCODE_X0 = 17,
V2CMPLTUI_IMM8_OPCODE_X1 = 42,
V2CMPLTU_RRR_0_OPCODE_X0 = 123,
V2CMPLTU_RRR_0_OPCODE_X1 = 79,
V2CMPNE_RRR_0_OPCODE_X0 = 124,
V2CMPNE_RRR_0_OPCODE_X1 = 80,
V2DOTPA_RRR_0_OPCODE_X0 = 125,
V2DOTP_RRR_0_OPCODE_X0 = 126,
V2INT_H_RRR_0_OPCODE_X0 = 127,
V2INT_H_RRR_0_OPCODE_X1 = 81,
V2INT_L_RRR_0_OPCODE_X0 = 128,
V2INT_L_RRR_0_OPCODE_X1 = 82,
V2MAXSI_IMM8_OPCODE_X0 = 18,
V2MAXSI_IMM8_OPCODE_X1 = 43,
V2MAXS_RRR_0_OPCODE_X0 = 129,
V2MAXS_RRR_0_OPCODE_X1 = 83,
V2MINSI_IMM8_OPCODE_X0 = 19,
V2MINSI_IMM8_OPCODE_X1 = 44,
V2MINS_RRR_0_OPCODE_X0 = 130,
V2MINS_RRR_0_OPCODE_X1 = 84,
V2MNZ_RRR_0_OPCODE_X0 = 131,
V2MNZ_RRR_0_OPCODE_X1 = 85,
V2MULFSC_RRR_0_OPCODE_X0 = 132,
V2MULS_RRR_0_OPCODE_X0 = 133,
V2MULTS_RRR_0_OPCODE_X0 = 134,
V2MZ_RRR_0_OPCODE_X0 = 135,
V2MZ_RRR_0_OPCODE_X1 = 86,
V2PACKH_RRR_0_OPCODE_X0 = 136,
V2PACKH_RRR_0_OPCODE_X1 = 87,
V2PACKL_RRR_0_OPCODE_X0 = 137,
V2PACKL_RRR_0_OPCODE_X1 = 88,
V2PACKUC_RRR_0_OPCODE_X0 = 138,
V2PACKUC_RRR_0_OPCODE_X1 = 89,
V2SADAS_RRR_0_OPCODE_X0 = 139,
V2SADAU_RRR_0_OPCODE_X0 = 140,
V2SADS_RRR_0_OPCODE_X0 = 141,
V2SADU_RRR_0_OPCODE_X0 = 142,
V2SHLI_SHIFT_OPCODE_X0 = 10,
V2SHLI_SHIFT_OPCODE_X1 = 10,
V2SHLSC_RRR_0_OPCODE_X0 = 143,
V2SHLSC_RRR_0_OPCODE_X1 = 90,
V2SHL_RRR_0_OPCODE_X0 = 144,
V2SHL_RRR_0_OPCODE_X1 = 91,
V2SHRSI_SHIFT_OPCODE_X0 = 11,
V2SHRSI_SHIFT_OPCODE_X1 = 11,
V2SHRS_RRR_0_OPCODE_X0 = 145,
V2SHRS_RRR_0_OPCODE_X1 = 92,
V2SHRUI_SHIFT_OPCODE_X0 = 12,
V2SHRUI_SHIFT_OPCODE_X1 = 12,
V2SHRU_RRR_0_OPCODE_X0 = 146,
V2SHRU_RRR_0_OPCODE_X1 = 93,
V2SUBSC_RRR_0_OPCODE_X0 = 147,
V2SUBSC_RRR_0_OPCODE_X1 = 94,
V2SUB_RRR_0_OPCODE_X0 = 148,
V2SUB_RRR_0_OPCODE_X1 = 95,
V4ADDSC_RRR_0_OPCODE_X0 = 149,
V4ADDSC_RRR_0_OPCODE_X1 = 96,
V4ADD_RRR_0_OPCODE_X0 = 150,
V4ADD_RRR_0_OPCODE_X1 = 97,
V4INT_H_RRR_0_OPCODE_X0 = 151,
V4INT_H_RRR_0_OPCODE_X1 = 98,
V4INT_L_RRR_0_OPCODE_X0 = 152,
V4INT_L_RRR_0_OPCODE_X1 = 99,
V4PACKSC_RRR_0_OPCODE_X0 = 153,
V4PACKSC_RRR_0_OPCODE_X1 = 100,
V4SHLSC_RRR_0_OPCODE_X0 = 154,
V4SHLSC_RRR_0_OPCODE_X1 = 101,
V4SHL_RRR_0_OPCODE_X0 = 155,
V4SHL_RRR_0_OPCODE_X1 = 102,
V4SHRS_RRR_0_OPCODE_X0 = 156,
V4SHRS_RRR_0_OPCODE_X1 = 103,
V4SHRU_RRR_0_OPCODE_X0 = 157,
V4SHRU_RRR_0_OPCODE_X1 = 104,
V4SUBSC_RRR_0_OPCODE_X0 = 158,
V4SUBSC_RRR_0_OPCODE_X1 = 105,
V4SUB_RRR_0_OPCODE_X0 = 159,
V4SUB_RRR_0_OPCODE_X1 = 106,
WH64_UNARY_OPCODE_X1 = 38,
XORI_IMM8_OPCODE_X0 = 20,
XORI_IMM8_OPCODE_X1 = 45,
XOR_RRR_0_OPCODE_X0 = 160,
XOR_RRR_0_OPCODE_X1 = 107,
XOR_RRR_5_OPCODE_Y0 = 3,
XOR_RRR_5_OPCODE_Y1 = 3
};
#endif /* !_TILE_OPCODE_CONSTANTS_H */

15
arch/tile/include/asm/opcode_constants.h → arch/tile/include/asm/tile-desc.h
View File

@ -1,5 +1,5 @@
/*
* Copyright 2010 Tilera Corporation. All Rights Reserved.
* Copyright 2011 Tilera Corporation. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
@ -12,15 +12,8 @@
* more details.
*/
#ifndef _ASM_TILE_OPCODE_CONSTANTS_H
#define _ASM_TILE_OPCODE_CONSTANTS_H
#include <arch/chip.h>
#if CHIP_WORD_SIZE() == 64
#include <asm/opcode_constants_64.h>
#ifndef __tilegx__
#include <asm/tile-desc_32.h>
#else
#include <asm/opcode_constants_32.h>
#include <asm/tile-desc_64.h>
#endif
#endif /* _ASM_TILE_OPCODE_CONSTANTS_H */

553
arch/tile/include/asm/tile-desc_32.h Normal file
View File

@ -0,0 +1,553 @@
/* TILEPro opcode information.
*
* Copyright 2011 Tilera Corporation. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation, version 2.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
* NON INFRINGEMENT. See the GNU General Public License for
* more details.
*
*
*
*
*
*/
#ifndef opcode_tilepro_h
#define opcode_tilepro_h
#include <arch/opcode.h>
enum
{
TILEPRO_MAX_OPERANDS = 5 /* mm */
};
typedef enum
{
TILEPRO_OPC_BPT,
TILEPRO_OPC_INFO,
TILEPRO_OPC_INFOL,
TILEPRO_OPC_J,
TILEPRO_OPC_JAL,
TILEPRO_OPC_MOVE,
TILEPRO_OPC_MOVE_SN,
TILEPRO_OPC_MOVEI,
TILEPRO_OPC_MOVEI_SN,
TILEPRO_OPC_MOVELI,
TILEPRO_OPC_MOVELI_SN,
TILEPRO_OPC_MOVELIS,
TILEPRO_OPC_PREFETCH,
TILEPRO_OPC_RAISE,
TILEPRO_OPC_ADD,
TILEPRO_OPC_ADD_SN,
TILEPRO_OPC_ADDB,
TILEPRO_OPC_ADDB_SN,
TILEPRO_OPC_ADDBS_U,
TILEPRO_OPC_ADDBS_U_SN,
TILEPRO_OPC_ADDH,
TILEPRO_OPC_ADDH_SN,
TILEPRO_OPC_ADDHS,
TILEPRO_OPC_ADDHS_SN,
TILEPRO_OPC_ADDI,
TILEPRO_OPC_ADDI_SN,
TILEPRO_OPC_ADDIB,
TILEPRO_OPC_ADDIB_SN,
TILEPRO_OPC_ADDIH,
TILEPRO_OPC_ADDIH_SN,
TILEPRO_OPC_ADDLI,
TILEPRO_OPC_ADDLI_SN,
TILEPRO_OPC_ADDLIS,
TILEPRO_OPC_ADDS,
TILEPRO_OPC_ADDS_SN,
TILEPRO_OPC_ADIFFB_U,
TILEPRO_OPC_ADIFFB_U_SN,
TILEPRO_OPC_ADIFFH,
TILEPRO_OPC_ADIFFH_SN,
TILEPRO_OPC_AND,
TILEPRO_OPC_AND_SN,
TILEPRO_OPC_ANDI,
TILEPRO_OPC_ANDI_SN,
TILEPRO_OPC_AULI,
TILEPRO_OPC_AVGB_U,
TILEPRO_OPC_AVGB_U_SN,
TILEPRO_OPC_AVGH,
TILEPRO_OPC_AVGH_SN,
TILEPRO_OPC_BBNS,
TILEPRO_OPC_BBNS_SN,
TILEPRO_OPC_BBNST,
TILEPRO_OPC_BBNST_SN,
TILEPRO_OPC_BBS,
TILEPRO_OPC_BBS_SN,
TILEPRO_OPC_BBST,
TILEPRO_OPC_BBST_SN,
TILEPRO_OPC_BGEZ,
TILEPRO_OPC_BGEZ_SN,
TILEPRO_OPC_BGEZT,
TILEPRO_OPC_BGEZT_SN,
TILEPRO_OPC_BGZ,
TILEPRO_OPC_BGZ_SN,
TILEPRO_OPC_BGZT,
TILEPRO_OPC_BGZT_SN,
TILEPRO_OPC_BITX,
TILEPRO_OPC_BITX_SN,
TILEPRO_OPC_BLEZ,
TILEPRO_OPC_BLEZ_SN,
TILEPRO_OPC_BLEZT,
TILEPRO_OPC_BLEZT_SN,
TILEPRO_OPC_BLZ,
TILEPRO_OPC_BLZ_SN,
TILEPRO_OPC_BLZT,
TILEPRO_OPC_BLZT_SN,
TILEPRO_OPC_BNZ,
TILEPRO_OPC_BNZ_SN,
TILEPRO_OPC_BNZT,
TILEPRO_OPC_BNZT_SN,
TILEPRO_OPC_BYTEX,
TILEPRO_OPC_BYTEX_SN,
TILEPRO_OPC_BZ,
TILEPRO_OPC_BZ_SN,
TILEPRO_OPC_BZT,
TILEPRO_OPC_BZT_SN,
TILEPRO_OPC_CLZ,
TILEPRO_OPC_CLZ_SN,
TILEPRO_OPC_CRC32_32,
TILEPRO_OPC_CRC32_32_SN,
TILEPRO_OPC_CRC32_8,
TILEPRO_OPC_CRC32_8_SN,
TILEPRO_OPC_CTZ,
TILEPRO_OPC_CTZ_SN,
TILEPRO_OPC_DRAIN,
TILEPRO_OPC_DTLBPR,
TILEPRO_OPC_DWORD_ALIGN,
TILEPRO_OPC_DWORD_ALIGN_SN,
TILEPRO_OPC_FINV,
TILEPRO_OPC_FLUSH,
TILEPRO_OPC_FNOP,
TILEPRO_OPC_ICOH,
TILEPRO_OPC_ILL,
TILEPRO_OPC_INTHB,
TILEPRO_OPC_INTHB_SN,
TILEPRO_OPC_INTHH,
TILEPRO_OPC_INTHH_SN,
TILEPRO_OPC_INTLB,
TILEPRO_OPC_INTLB_SN,
TILEPRO_OPC_INTLH,
TILEPRO_OPC_INTLH_SN,
TILEPRO_OPC_INV,
TILEPRO_OPC_IRET,
TILEPRO_OPC_JALB,
TILEPRO_OPC_JALF,
TILEPRO_OPC_JALR,
TILEPRO_OPC_JALRP,
TILEPRO_OPC_JB,
TILEPRO_OPC_JF,
TILEPRO_OPC_JR,
TILEPRO_OPC_JRP,
TILEPRO_OPC_LB,
TILEPRO_OPC_LB_SN,
TILEPRO_OPC_LB_U,
TILEPRO_OPC_LB_U_SN,
TILEPRO_OPC_LBADD,
TILEPRO_OPC_LBADD_SN,
TILEPRO_OPC_LBADD_U,
TILEPRO_OPC_LBADD_U_SN,
TILEPRO_OPC_LH,
TILEPRO_OPC_LH_SN,
TILEPRO_OPC_LH_U,
TILEPRO_OPC_LH_U_SN,
TILEPRO_OPC_LHADD,
TILEPRO_OPC_LHADD_SN,
TILEPRO_OPC_LHADD_U,
TILEPRO_OPC_LHADD_U_SN,
TILEPRO_OPC_LNK,
TILEPRO_OPC_LNK_SN,
TILEPRO_OPC_LW,
TILEPRO_OPC_LW_SN,
TILEPRO_OPC_LW_NA,
TILEPRO_OPC_LW_NA_SN,
TILEPRO_OPC_LWADD,
TILEPRO_OPC_LWADD_SN,
TILEPRO_OPC_LWADD_NA,
TILEPRO_OPC_LWADD_NA_SN,
TILEPRO_OPC_MAXB_U,
TILEPRO_OPC_MAXB_U_SN,
TILEPRO_OPC_MAXH,
TILEPRO_OPC_MAXH_SN,
TILEPRO_OPC_MAXIB_U,
TILEPRO_OPC_MAXIB_U_SN,
TILEPRO_OPC_MAXIH,
TILEPRO_OPC_MAXIH_SN,
TILEPRO_OPC_MF,
TILEPRO_OPC_MFSPR,
TILEPRO_OPC_MINB_U,
TILEPRO_OPC_MINB_U_SN,
TILEPRO_OPC_MINH,
TILEPRO_OPC_MINH_SN,
TILEPRO_OPC_MINIB_U,
TILEPRO_OPC_MINIB_U_SN,
TILEPRO_OPC_MINIH,
TILEPRO_OPC_MINIH_SN,
TILEPRO_OPC_MM,
TILEPRO_OPC_MNZ,
TILEPRO_OPC_MNZ_SN,
TILEPRO_OPC_MNZB,
TILEPRO_OPC_MNZB_SN,
TILEPRO_OPC_MNZH,
TILEPRO_OPC_MNZH_SN,
TILEPRO_OPC_MTSPR,
TILEPRO_OPC_MULHH_SS,
TILEPRO_OPC_MULHH_SS_SN,
TILEPRO_OPC_MULHH_SU,
TILEPRO_OPC_MULHH_SU_SN,
TILEPRO_OPC_MULHH_UU,
TILEPRO_OPC_MULHH_UU_SN,
TILEPRO_OPC_MULHHA_SS,
TILEPRO_OPC_MULHHA_SS_SN,
TILEPRO_OPC_MULHHA_SU,
TILEPRO_OPC_MULHHA_SU_SN,
TILEPRO_OPC_MULHHA_UU,
TILEPRO_OPC_MULHHA_UU_SN,
TILEPRO_OPC_MULHHSA_UU,
TILEPRO_OPC_MULHHSA_UU_SN,
TILEPRO_OPC_MULHL_SS,
TILEPRO_OPC_MULHL_SS_SN,
TILEPRO_OPC_MULHL_SU,
TILEPRO_OPC_MULHL_SU_SN,
TILEPRO_OPC_MULHL_US,
TILEPRO_OPC_MULHL_US_SN,
TILEPRO_OPC_MULHL_UU,
TILEPRO_OPC_MULHL_UU_SN,
TILEPRO_OPC_MULHLA_SS,
TILEPRO_OPC_MULHLA_SS_SN,
TILEPRO_OPC_MULHLA_SU,
TILEPRO_OPC_MULHLA_SU_SN,
TILEPRO_OPC_MULHLA_US,
TILEPRO_OPC_MULHLA_US_SN,
TILEPRO_OPC_MULHLA_UU,
TILEPRO_OPC_MULHLA_UU_SN,
TILEPRO_OPC_MULHLSA_UU,
TILEPRO_OPC_MULHLSA_UU_SN,
TILEPRO_OPC_MULLL_SS,
TILEPRO_OPC_MULLL_SS_SN,
TILEPRO_OPC_MULLL_SU,
TILEPRO_OPC_MULLL_SU_SN,
TILEPRO_OPC_MULLL_UU,
TILEPRO_OPC_MULLL_UU_SN,
TILEPRO_OPC_MULLLA_SS,
TILEPRO_OPC_MULLLA_SS_SN,
TILEPRO_OPC_MULLLA_SU,
TILEPRO_OPC_MULLLA_SU_SN,
TILEPRO_OPC_MULLLA_UU,
TILEPRO_OPC_MULLLA_UU_SN,
TILEPRO_OPC_MULLLSA_UU,
TILEPRO_OPC_MULLLSA_UU_SN,
TILEPRO_OPC_MVNZ,
TILEPRO_OPC_MVNZ_SN,
TILEPRO_OPC_MVZ,
TILEPRO_OPC_MVZ_SN,
TILEPRO_OPC_MZ,
TILEPRO_OPC_MZ_SN,
TILEPRO_OPC_MZB,
TILEPRO_OPC_MZB_SN,
TILEPRO_OPC_MZH,
TILEPRO_OPC_MZH_SN,
TILEPRO_OPC_NAP,
TILEPRO_OPC_NOP,
TILEPRO_OPC_NOR,
TILEPRO_OPC_NOR_SN,
TILEPRO_OPC_OR,
TILEPRO_OPC_OR_SN,
TILEPRO_OPC_ORI,
TILEPRO_OPC_ORI_SN,
TILEPRO_OPC_PACKBS_U,
TILEPRO_OPC_PACKBS_U_SN,
TILEPRO_OPC_PACKHB,
TILEPRO_OPC_PACKHB_SN,
TILEPRO_OPC_PACKHS,
TILEPRO_OPC_PACKHS_SN,
TILEPRO_OPC_PACKLB,
TILEPRO_OPC_PACKLB_SN,
TILEPRO_OPC_PCNT,
TILEPRO_OPC_PCNT_SN,
TILEPRO_OPC_RL,
TILEPRO_OPC_RL_SN,
TILEPRO_OPC_RLI,
TILEPRO_OPC_RLI_SN,
TILEPRO_OPC_S1A,
TILEPRO_OPC_S1A_SN,
TILEPRO_OPC_S2A,
TILEPRO_OPC_S2A_SN,
TILEPRO_OPC_S3A,
TILEPRO_OPC_S3A_SN,
TILEPRO_OPC_SADAB_U,
TILEPRO_OPC_SADAB_U_SN,
TILEPRO_OPC_SADAH,
TILEPRO_OPC_SADAH_SN,
TILEPRO_OPC_SADAH_U,
TILEPRO_OPC_SADAH_U_SN,
TILEPRO_OPC_SADB_U,
TILEPRO_OPC_SADB_U_SN,
TILEPRO_OPC_SADH,
TILEPRO_OPC_SADH_SN,
TILEPRO_OPC_SADH_U,
TILEPRO_OPC_SADH_U_SN,
TILEPRO_OPC_SB,
TILEPRO_OPC_SBADD,
TILEPRO_OPC_SEQ,
TILEPRO_OPC_SEQ_SN,
TILEPRO_OPC_SEQB,
TILEPRO_OPC_SEQB_SN,
TILEPRO_OPC_SEQH,
TILEPRO_OPC_SEQH_SN,
TILEPRO_OPC_SEQI,
TILEPRO_OPC_SEQI_SN,
TILEPRO_OPC_SEQIB,
TILEPRO_OPC_SEQIB_SN,
TILEPRO_OPC_SEQIH,
TILEPRO_OPC_SEQIH_SN,
TILEPRO_OPC_SH,
TILEPRO_OPC_SHADD,
TILEPRO_OPC_SHL,
TILEPRO_OPC_SHL_SN,
TILEPRO_OPC_SHLB,
TILEPRO_OPC_SHLB_SN,
TILEPRO_OPC_SHLH,
TILEPRO_OPC_SHLH_SN,
TILEPRO_OPC_SHLI,
TILEPRO_OPC_SHLI_SN,
TILEPRO_OPC_SHLIB,
TILEPRO_OPC_SHLIB_SN,
TILEPRO_OPC_SHLIH,
TILEPRO_OPC_SHLIH_SN,
TILEPRO_OPC_SHR,
TILEPRO_OPC_SHR_SN,
TILEPRO_OPC_SHRB,
TILEPRO_OPC_SHRB_SN,
TILEPRO_OPC_SHRH,
TILEPRO_OPC_SHRH_SN,
TILEPRO_OPC_SHRI,
TILEPRO_OPC_SHRI_SN,
TILEPRO_OPC_SHRIB,
TILEPRO_OPC_SHRIB_SN,
TILEPRO_OPC_SHRIH,
TILEPRO_OPC_SHRIH_SN,
TILEPRO_OPC_SLT,
TILEPRO_OPC_SLT_SN,
TILEPRO_OPC_SLT_U,
TILEPRO_OPC_SLT_U_SN,
TILEPRO_OPC_SLTB,
TILEPRO_OPC_SLTB_SN,
TILEPRO_OPC_SLTB_U,
TILEPRO_OPC_SLTB_U_SN,
TILEPRO_OPC_SLTE,
TILEPRO_OPC_SLTE_SN,
TILEPRO_OPC_SLTE_U,
TILEPRO_OPC_SLTE_U_SN,
TILEPRO_OPC_SLTEB,
TILEPRO_OPC_SLTEB_SN,
TILEPRO_OPC_SLTEB_U,
TILEPRO_OPC_SLTEB_U_SN,
TILEPRO_OPC_SLTEH,
TILEPRO_OPC_SLTEH_SN,
TILEPRO_OPC_SLTEH_U,
TILEPRO_OPC_SLTEH_U_SN,
TILEPRO_OPC_SLTH,
TILEPRO_OPC_SLTH_SN,
TILEPRO_OPC_SLTH_U,
TILEPRO_OPC_SLTH_U_SN,
TILEPRO_OPC_SLTI,
TILEPRO_OPC_SLTI_SN,
TILEPRO_OPC_SLTI_U,
TILEPRO_OPC_SLTI_U_SN,
TILEPRO_OPC_SLTIB,
TILEPRO_OPC_SLTIB_SN,
TILEPRO_OPC_SLTIB_U,
TILEPRO_OPC_SLTIB_U_SN,
TILEPRO_OPC_SLTIH,
TILEPRO_OPC_SLTIH_SN,
TILEPRO_OPC_SLTIH_U,
TILEPRO_OPC_SLTIH_U_SN,
TILEPRO_OPC_SNE,
TILEPRO_OPC_SNE_SN,
TILEPRO_OPC_SNEB,
TILEPRO_OPC_SNEB_SN,
TILEPRO_OPC_SNEH,
TILEPRO_OPC_SNEH_SN,
TILEPRO_OPC_SRA,
TILEPRO_OPC_SRA_SN,
TILEPRO_OPC_SRAB,
TILEPRO_OPC_SRAB_SN,
TILEPRO_OPC_SRAH,
TILEPRO_OPC_SRAH_SN,
TILEPRO_OPC_SRAI,
TILEPRO_OPC_SRAI_SN,
TILEPRO_OPC_SRAIB,
TILEPRO_OPC_SRAIB_SN,
TILEPRO_OPC_SRAIH,
TILEPRO_OPC_SRAIH_SN,
TILEPRO_OPC_SUB,
TILEPRO_OPC_SUB_SN,
TILEPRO_OPC_SUBB,
TILEPRO_OPC_SUBB_SN,
TILEPRO_OPC_SUBBS_U,
TILEPRO_OPC_SUBBS_U_SN,
TILEPRO_OPC_SUBH,
TILEPRO_OPC_SUBH_SN,
TILEPRO_OPC_SUBHS,
TILEPRO_OPC_SUBHS_SN,
TILEPRO_OPC_SUBS,
TILEPRO_OPC_SUBS_SN,
TILEPRO_OPC_SW,
TILEPRO_OPC_SWADD,
TILEPRO_OPC_SWINT0,
TILEPRO_OPC_SWINT1,
TILEPRO_OPC_SWINT2,
TILEPRO_OPC_SWINT3,
TILEPRO_OPC_TBLIDXB0,
TILEPRO_OPC_TBLIDXB0_SN,
TILEPRO_OPC_TBLIDXB1,
TILEPRO_OPC_TBLIDXB1_SN,
TILEPRO_OPC_TBLIDXB2,
TILEPRO_OPC_TBLIDXB2_SN,
TILEPRO_OPC_TBLIDXB3,
TILEPRO_OPC_TBLIDXB3_SN,
TILEPRO_OPC_TNS,
TILEPRO_OPC_TNS_SN,
TILEPRO_OPC_WH64,
TILEPRO_OPC_XOR,
TILEPRO_OPC_XOR_SN,
TILEPRO_OPC_XORI,
TILEPRO_OPC_XORI_SN,
TILEPRO_OPC_NONE
} tilepro_mnemonic;
typedef enum
{
TILEPRO_PIPELINE_X0,
TILEPRO_PIPELINE_X1,
TILEPRO_PIPELINE_Y0,
TILEPRO_PIPELINE_Y1,
TILEPRO_PIPELINE_Y2,
} tilepro_pipeline;
#define tilepro_is_x_pipeline(p) ((int)(p) <= (int)TILEPRO_PIPELINE_X1)
typedef enum
{
TILEPRO_OP_TYPE_REGISTER,
TILEPRO_OP_TYPE_IMMEDIATE,
TILEPRO_OP_TYPE_ADDRESS,
TILEPRO_OP_TYPE_SPR
} tilepro_operand_type;
struct tilepro_operand
{
/* Is this operand a register, immediate or address? */
tilepro_operand_type type;
/* The default relocation type for this operand. */
signed int default_reloc : 16;
/* How many bits is this value? (used for range checking) */
unsigned int num_bits : 5;
/* Is the value signed? (used for range checking) */
unsigned int is_signed : 1;
/* Is this operand a source register? */
unsigned int is_src_reg : 1;
/* Is this operand written? (i.e. is it a destination register) */
unsigned int is_dest_reg : 1;
/* Is this operand PC-relative? */
unsigned int is_pc_relative : 1;
/* By how many bits do we right shift the value before inserting? */
unsigned int rightshift : 2;
/* Return the bits for this operand to be ORed into an existing bundle. */
tilepro_bundle_bits (*insert) (int op);
/* Extract this operand and return it. */
unsigned int (*extract) (tilepro_bundle_bits bundle);
};
extern const struct tilepro_operand tilepro_operands[];
/* One finite-state machine per pipe for rapid instruction decoding. */
extern const unsigned short * const
tilepro_bundle_decoder_fsms[TILEPRO_NUM_PIPELINE_ENCODINGS];
struct tilepro_opcode
{
/* The opcode mnemonic, e.g. "add" */
const char *name;
/* The enum value for this mnemonic. */
tilepro_mnemonic mnemonic;
/* A bit mask of which of the five pipes this instruction
is compatible with:
X0 0x01
X1 0x02
Y0 0x04
Y1 0x08
Y2 0x10 */
unsigned char pipes;
/* How many operands are there? */
unsigned char num_operands;
/* Which register does this write implicitly, or TREG_ZERO if none? */
unsigned char implicitly_written_register;
/* Can this be bundled with other instructions (almost always true). */
unsigned char can_bundle;
/* The description of the operands. Each of these is an
* index into the tilepro_operands[] table. */
unsigned char operands[TILEPRO_NUM_PIPELINE_ENCODINGS][TILEPRO_MAX_OPERANDS];
};
extern const struct tilepro_opcode tilepro_opcodes[];
/* Used for non-textual disassembly into structs. */
struct tilepro_decoded_instruction
{
const struct tilepro_opcode *opcode;
const struct tilepro_operand *operands[TILEPRO_MAX_OPERANDS];
int operand_values[TILEPRO_MAX_OPERANDS];
};
/* Disassemble a bundle into a struct for machine processing. */
extern int parse_insn_tilepro(tilepro_bundle_bits bits,
unsigned int pc,
struct tilepro_decoded_instruction
decoded[TILEPRO_MAX_INSTRUCTIONS_PER_BUNDLE]);
/* Given a set of bundle bits and a specific pipe, returns which
* instruction the bundle contains in that pipe.
*/
extern const struct tilepro_opcode *
find_opcode(tilepro_bundle_bits bits, tilepro_pipeline pipe);
#endif /* opcode_tilepro_h */

483
arch/tile/include/asm/tile-desc_64.h Normal file
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@ -0,0 +1,483 @@
/* TILE-Gx opcode information.
*
* Copyright 2011 Tilera Corporation. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation, version 2.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
* NON INFRINGEMENT. See the GNU General Public License for
* more details.
*
*
*
*
*
*/
#ifndef opcode_tile_h
#define opcode_tile_h
#include <arch/opcode.h>
enum
{
TILEGX_MAX_OPERANDS = 4 /* bfexts */
};
typedef enum
{
TILEGX_OPC_BPT,
TILEGX_OPC_INFO,
TILEGX_OPC_INFOL,
TILEGX_OPC_MOVE,
TILEGX_OPC_MOVEI,
TILEGX_OPC_MOVELI,
TILEGX_OPC_PREFETCH,
TILEGX_OPC_PREFETCH_ADD_L1,
TILEGX_OPC_PREFETCH_ADD_L1_FAULT,
TILEGX_OPC_PREFETCH_ADD_L2,
TILEGX_OPC_PREFETCH_ADD_L2_FAULT,
TILEGX_OPC_PREFETCH_ADD_L3,
TILEGX_OPC_PREFETCH_ADD_L3_FAULT,
TILEGX_OPC_PREFETCH_L1,
TILEGX_OPC_PREFETCH_L1_FAULT,
TILEGX_OPC_PREFETCH_L2,
TILEGX_OPC_PREFETCH_L2_FAULT,
TILEGX_OPC_PREFETCH_L3,
TILEGX_OPC_PREFETCH_L3_FAULT,
TILEGX_OPC_RAISE,
TILEGX_OPC_ADD,
TILEGX_OPC_ADDI,
TILEGX_OPC_ADDLI,
TILEGX_OPC_ADDX,
TILEGX_OPC_ADDXI,
TILEGX_OPC_ADDXLI,
TILEGX_OPC_ADDXSC,
TILEGX_OPC_AND,
TILEGX_OPC_ANDI,
TILEGX_OPC_BEQZ,
TILEGX_OPC_BEQZT,
TILEGX_OPC_BFEXTS,
TILEGX_OPC_BFEXTU,
TILEGX_OPC_BFINS,
TILEGX_OPC_BGEZ,
TILEGX_OPC_BGEZT,
TILEGX_OPC_BGTZ,
TILEGX_OPC_BGTZT,
TILEGX_OPC_BLBC,
TILEGX_OPC_BLBCT,
TILEGX_OPC_BLBS,
TILEGX_OPC_BLBST,
TILEGX_OPC_BLEZ,
TILEGX_OPC_BLEZT,
TILEGX_OPC_BLTZ,
TILEGX_OPC_BLTZT,
TILEGX_OPC_BNEZ,
TILEGX_OPC_BNEZT,
TILEGX_OPC_CLZ,
TILEGX_OPC_CMOVEQZ,
TILEGX_OPC_CMOVNEZ,
TILEGX_OPC_CMPEQ,
TILEGX_OPC_CMPEQI,
TILEGX_OPC_CMPEXCH,
TILEGX_OPC_CMPEXCH4,
TILEGX_OPC_CMPLES,
TILEGX_OPC_CMPLEU,
TILEGX_OPC_CMPLTS,
TILEGX_OPC_CMPLTSI,
TILEGX_OPC_CMPLTU,
TILEGX_OPC_CMPLTUI,
TILEGX_OPC_CMPNE,
TILEGX_OPC_CMUL,
TILEGX_OPC_CMULA,
TILEGX_OPC_CMULAF,
TILEGX_OPC_CMULF,
TILEGX_OPC_CMULFR,
TILEGX_OPC_CMULH,
TILEGX_OPC_CMULHR,
TILEGX_OPC_CRC32_32,
TILEGX_OPC_CRC32_8,
TILEGX_OPC_CTZ,
TILEGX_OPC_DBLALIGN,
TILEGX_OPC_DBLALIGN2,
TILEGX_OPC_DBLALIGN4,
TILEGX_OPC_DBLALIGN6,
TILEGX_OPC_DRAIN,
TILEGX_OPC_DTLBPR,
TILEGX_OPC_EXCH,
TILEGX_OPC_EXCH4,
TILEGX_OPC_FDOUBLE_ADD_FLAGS,
TILEGX_OPC_FDOUBLE_ADDSUB,
TILEGX_OPC_FDOUBLE_MUL_FLAGS,
TILEGX_OPC_FDOUBLE_PACK1,
TILEGX_OPC_FDOUBLE_PACK2,
TILEGX_OPC_FDOUBLE_SUB_FLAGS,
TILEGX_OPC_FDOUBLE_UNPACK_MAX,
TILEGX_OPC_FDOUBLE_UNPACK_MIN,
TILEGX_OPC_FETCHADD,
TILEGX_OPC_FETCHADD4,
TILEGX_OPC_FETCHADDGEZ,
TILEGX_OPC_FETCHADDGEZ4,
TILEGX_OPC_FETCHAND,
TILEGX_OPC_FETCHAND4,
TILEGX_OPC_FETCHOR,
TILEGX_OPC_FETCHOR4,
TILEGX_OPC_FINV,
TILEGX_OPC_FLUSH,
TILEGX_OPC_FLUSHWB,
TILEGX_OPC_FNOP,
TILEGX_OPC_FSINGLE_ADD1,
TILEGX_OPC_FSINGLE_ADDSUB2,
TILEGX_OPC_FSINGLE_MUL1,
TILEGX_OPC_FSINGLE_MUL2,
TILEGX_OPC_FSINGLE_PACK1,
TILEGX_OPC_FSINGLE_PACK2,
TILEGX_OPC_FSINGLE_SUB1,
TILEGX_OPC_ICOH,
TILEGX_OPC_ILL,
TILEGX_OPC_INV,
TILEGX_OPC_IRET,
TILEGX_OPC_J,
TILEGX_OPC_JAL,
TILEGX_OPC_JALR,
TILEGX_OPC_JALRP,
TILEGX_OPC_JR,
TILEGX_OPC_JRP,
TILEGX_OPC_LD,
TILEGX_OPC_LD1S,
TILEGX_OPC_LD1S_ADD,
TILEGX_OPC_LD1U,
TILEGX_OPC_LD1U_ADD,
TILEGX_OPC_LD2S,
TILEGX_OPC_LD2S_ADD,
TILEGX_OPC_LD2U,
TILEGX_OPC_LD2U_ADD,
TILEGX_OPC_LD4S,
TILEGX_OPC_LD4S_ADD,
TILEGX_OPC_LD4U,
TILEGX_OPC_LD4U_ADD,
TILEGX_OPC_LD_ADD,
TILEGX_OPC_LDNA,
TILEGX_OPC_LDNA_ADD,
TILEGX_OPC_LDNT,
TILEGX_OPC_LDNT1S,
TILEGX_OPC_LDNT1S_ADD,
TILEGX_OPC_LDNT1U,
TILEGX_OPC_LDNT1U_ADD,
TILEGX_OPC_LDNT2S,
TILEGX_OPC_LDNT2S_ADD,
TILEGX_OPC_LDNT2U,
TILEGX_OPC_LDNT2U_ADD,
TILEGX_OPC_LDNT4S,
TILEGX_OPC_LDNT4S_ADD,
TILEGX_OPC_LDNT4U,
TILEGX_OPC_LDNT4U_ADD,
TILEGX_OPC_LDNT_ADD,
TILEGX_OPC_LNK,
TILEGX_OPC_MF,
TILEGX_OPC_MFSPR,
TILEGX_OPC_MM,
TILEGX_OPC_MNZ,
TILEGX_OPC_MTSPR,
TILEGX_OPC_MUL_HS_HS,
TILEGX_OPC_MUL_HS_HU,
TILEGX_OPC_MUL_HS_LS,
TILEGX_OPC_MUL_HS_LU,
TILEGX_OPC_MUL_HU_HU,
TILEGX_OPC_MUL_HU_LS,
TILEGX_OPC_MUL_HU_LU,
TILEGX_OPC_MUL_LS_LS,
TILEGX_OPC_MUL_LS_LU,
TILEGX_OPC_MUL_LU_LU,
TILEGX_OPC_MULA_HS_HS,
TILEGX_OPC_MULA_HS_HU,
TILEGX_OPC_MULA_HS_LS,
TILEGX_OPC_MULA_HS_LU,
TILEGX_OPC_MULA_HU_HU,
TILEGX_OPC_MULA_HU_LS,
TILEGX_OPC_MULA_HU_LU,
TILEGX_OPC_MULA_LS_LS,
TILEGX_OPC_MULA_LS_LU,
TILEGX_OPC_MULA_LU_LU,
TILEGX_OPC_MULAX,
TILEGX_OPC_MULX,
TILEGX_OPC_MZ,
TILEGX_OPC_NAP,
TILEGX_OPC_NOP,
TILEGX_OPC_NOR,
TILEGX_OPC_OR,
TILEGX_OPC_ORI,
TILEGX_OPC_PCNT,
TILEGX_OPC_REVBITS,
TILEGX_OPC_REVBYTES,
TILEGX_OPC_ROTL,
TILEGX_OPC_ROTLI,
TILEGX_OPC_SHL,
TILEGX_OPC_SHL16INSLI,
TILEGX_OPC_SHL1ADD,
TILEGX_OPC_SHL1ADDX,
TILEGX_OPC_SHL2ADD,
TILEGX_OPC_SHL2ADDX,
TILEGX_OPC_SHL3ADD,
TILEGX_OPC_SHL3ADDX,
TILEGX_OPC_SHLI,
TILEGX_OPC_SHLX,
TILEGX_OPC_SHLXI,
TILEGX_OPC_SHRS,
TILEGX_OPC_SHRSI,
TILEGX_OPC_SHRU,
TILEGX_OPC_SHRUI,
TILEGX_OPC_SHRUX,
TILEGX_OPC_SHRUXI,
TILEGX_OPC_SHUFFLEBYTES,
TILEGX_OPC_ST,
TILEGX_OPC_ST1,
TILEGX_OPC_ST1_ADD,
TILEGX_OPC_ST2,
TILEGX_OPC_ST2_ADD,
TILEGX_OPC_ST4,
TILEGX_OPC_ST4_ADD,
TILEGX_OPC_ST_ADD,
TILEGX_OPC_STNT,
TILEGX_OPC_STNT1,
TILEGX_OPC_STNT1_ADD,
TILEGX_OPC_STNT2,
TILEGX_OPC_STNT2_ADD,
TILEGX_OPC_STNT4,
TILEGX_OPC_STNT4_ADD,
TILEGX_OPC_STNT_ADD,
TILEGX_OPC_SUB,
TILEGX_OPC_SUBX,
TILEGX_OPC_SUBXSC,
TILEGX_OPC_SWINT0,
TILEGX_OPC_SWINT1,
TILEGX_OPC_SWINT2,
TILEGX_OPC_SWINT3,
TILEGX_OPC_TBLIDXB0,
TILEGX_OPC_TBLIDXB1,
TILEGX_OPC_TBLIDXB2,
TILEGX_OPC_TBLIDXB3,
TILEGX_OPC_V1ADD,
TILEGX_OPC_V1ADDI,
TILEGX_OPC_V1ADDUC,
TILEGX_OPC_V1ADIFFU,
TILEGX_OPC_V1AVGU,
TILEGX_OPC_V1CMPEQ,
TILEGX_OPC_V1CMPEQI,
TILEGX_OPC_V1CMPLES,
TILEGX_OPC_V1CMPLEU,
TILEGX_OPC_V1CMPLTS,
TILEGX_OPC_V1CMPLTSI,
TILEGX_OPC_V1CMPLTU,
TILEGX_OPC_V1CMPLTUI,
TILEGX_OPC_V1CMPNE,
TILEGX_OPC_V1DDOTPU,
TILEGX_OPC_V1DDOTPUA,
TILEGX_OPC_V1DDOTPUS,
TILEGX_OPC_V1DDOTPUSA,
TILEGX_OPC_V1DOTP,
TILEGX_OPC_V1DOTPA,
TILEGX_OPC_V1DOTPU,
TILEGX_OPC_V1DOTPUA,
TILEGX_OPC_V1DOTPUS,
TILEGX_OPC_V1DOTPUSA,
TILEGX_OPC_V1INT_H,
TILEGX_OPC_V1INT_L,
TILEGX_OPC_V1MAXU,
TILEGX_OPC_V1MAXUI,
TILEGX_OPC_V1MINU,
TILEGX_OPC_V1MINUI,
TILEGX_OPC_V1MNZ,
TILEGX_OPC_V1MULTU,
TILEGX_OPC_V1MULU,
TILEGX_OPC_V1MULUS,
TILEGX_OPC_V1MZ,
TILEGX_OPC_V1SADAU,
TILEGX_OPC_V1SADU,
TILEGX_OPC_V1SHL,
TILEGX_OPC_V1SHLI,
TILEGX_OPC_V1SHRS,
TILEGX_OPC_V1SHRSI,
TILEGX_OPC_V1SHRU,
TILEGX_OPC_V1SHRUI,
TILEGX_OPC_V1SUB,
TILEGX_OPC_V1SUBUC,
TILEGX_OPC_V2ADD,
TILEGX_OPC_V2ADDI,
TILEGX_OPC_V2ADDSC,
TILEGX_OPC_V2ADIFFS,
TILEGX_OPC_V2AVGS,
TILEGX_OPC_V2CMPEQ,
TILEGX_OPC_V2CMPEQI,
TILEGX_OPC_V2CMPLES,
TILEGX_OPC_V2CMPLEU,
TILEGX_OPC_V2CMPLTS,
TILEGX_OPC_V2CMPLTSI,
TILEGX_OPC_V2CMPLTU,
TILEGX_OPC_V2CMPLTUI,
TILEGX_OPC_V2CMPNE,
TILEGX_OPC_V2DOTP,
TILEGX_OPC_V2DOTPA,
TILEGX_OPC_V2INT_H,
TILEGX_OPC_V2INT_L,
TILEGX_OPC_V2MAXS,
TILEGX_OPC_V2MAXSI,
TILEGX_OPC_V2MINS,
TILEGX_OPC_V2MINSI,
TILEGX_OPC_V2MNZ,
TILEGX_OPC_V2MULFSC,
TILEGX_OPC_V2MULS,
TILEGX_OPC_V2MULTS,
TILEGX_OPC_V2MZ,
TILEGX_OPC_V2PACKH,
TILEGX_OPC_V2PACKL,
TILEGX_OPC_V2PACKUC,
TILEGX_OPC_V2SADAS,
TILEGX_OPC_V2SADAU,
TILEGX_OPC_V2SADS,
TILEGX_OPC_V2SADU,
TILEGX_OPC_V2SHL,
TILEGX_OPC_V2SHLI,
TILEGX_OPC_V2SHLSC,
TILEGX_OPC_V2SHRS,
TILEGX_OPC_V2SHRSI,
TILEGX_OPC_V2SHRU,
TILEGX_OPC_V2SHRUI,
TILEGX_OPC_V2SUB,
TILEGX_OPC_V2SUBSC,
TILEGX_OPC_V4ADD,
TILEGX_OPC_V4ADDSC,
TILEGX_OPC_V4INT_H,
TILEGX_OPC_V4INT_L,
TILEGX_OPC_V4PACKSC,
TILEGX_OPC_V4SHL,
TILEGX_OPC_V4SHLSC,
TILEGX_OPC_V4SHRS,
TILEGX_OPC_V4SHRU,
TILEGX_OPC_V4SUB,
TILEGX_OPC_V4SUBSC,
TILEGX_OPC_WH64,
TILEGX_OPC_XOR,
TILEGX_OPC_XORI,
TILEGX_OPC_NONE
} tilegx_mnemonic;
typedef enum
{
TILEGX_PIPELINE_X0,
TILEGX_PIPELINE_X1,
TILEGX_PIPELINE_Y0,
TILEGX_PIPELINE_Y1,
TILEGX_PIPELINE_Y2,
} tilegx_pipeline;
#define tilegx_is_x_pipeline(p) ((int)(p) <= (int)TILEGX_PIPELINE_X1)
typedef enum
{
TILEGX_OP_TYPE_REGISTER,
TILEGX_OP_TYPE_IMMEDIATE,
TILEGX_OP_TYPE_ADDRESS,
TILEGX_OP_TYPE_SPR
} tilegx_operand_type;
struct tilegx_operand
{
/* Is this operand a register, immediate or address? */
tilegx_operand_type type;
/* The default relocation type for this operand. */
signed int default_reloc : 16;
/* How many bits is this value? (used for range checking) */
unsigned int num_bits : 5;
/* Is the value signed? (used for range checking) */
unsigned int is_signed : 1;
/* Is this operand a source register? */
unsigned int is_src_reg : 1;
/* Is this operand written? (i.e. is it a destination register) */
unsigned int is_dest_reg : 1;
/* Is this operand PC-relative? */
unsigned int is_pc_relative : 1;
/* By how many bits do we right shift the value before inserting? */
unsigned int rightshift : 2;
/* Return the bits for this operand to be ORed into an existing bundle. */
tilegx_bundle_bits (*insert) (int op);
/* Extract this operand and return it. */
unsigned int (*extract) (tilegx_bundle_bits bundle);
};
extern const struct tilegx_operand tilegx_operands[];
/* One finite-state machine per pipe for rapid instruction decoding. */
extern const unsigned short * const
tilegx_bundle_decoder_fsms[TILEGX_NUM_PIPELINE_ENCODINGS];
struct tilegx_opcode
{
/* The opcode mnemonic, e.g. "add" */
const char *name;
/* The enum value for this mnemonic. */
tilegx_mnemonic mnemonic;
/* A bit mask of which of the five pipes this instruction
is compatible with:
X0 0x01
X1 0x02
Y0 0x04
Y1 0x08
Y2 0x10 */
unsigned char pipes;
/* How many operands are there? */
unsigned char num_operands;
/* Which register does this write implicitly, or TREG_ZERO if none? */
unsigned char implicitly_written_register;
/* Can this be bundled with other instructions (almost always true). */
unsigned char can_bundle;
/* The description of the operands. Each of these is an
* index into the tilegx_operands[] table. */
unsigned char operands[TILEGX_NUM_PIPELINE_ENCODINGS][TILEGX_MAX_OPERANDS];
};
extern const struct tilegx_opcode tilegx_opcodes[];
/* Used for non-textual disassembly into structs. */
struct tilegx_decoded_instruction
{
const struct tilegx_opcode *opcode;
const struct tilegx_operand *operands[TILEGX_MAX_OPERANDS];
long long operand_values[TILEGX_MAX_OPERANDS];
};
/* Disassemble a bundle into a struct for machine processing. */
extern int parse_insn_tilegx(tilegx_bundle_bits bits,
unsigned long long pc,
struct tilegx_decoded_instruction
decoded[TILEGX_MAX_INSTRUCTIONS_PER_BUNDLE]);
#endif /* opcode_tilegx_h */