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drm/nvc0/pfifo: support for chipsets with only one PSUBFIFO (0xc1)

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Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs
2010-12-31 12:10:49 +10:00
parent 2a55c9a7ff
commit ec9c0883ea
1 changed files with 12 additions and 6 deletions
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18
drivers/gpu/drm/nouveau/nvc0_fifo.c
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@@ -33,6 +33,7 @@ struct nvc0_fifo_priv {
struct nouveau_gpuobj *playlist[2]; struct nouveau_gpuobj *playlist[2];
int cur_playlist; int cur_playlist;
struct nouveau_vma user_vma; struct nouveau_vma user_vma;
int spoon_nr;
}; };
struct nvc0_fifo_chan { struct nvc0_fifo_chan {
@@ -324,13 +325,18 @@ nvc0_fifo_init(struct drm_device *dev)
nv_wr32(dev, 0x000204, 0xffffffff); nv_wr32(dev, 0x000204, 0xffffffff);
nv_wr32(dev, 0x002204, 0xffffffff); nv_wr32(dev, 0x002204, 0xffffffff);
priv->spoon_nr = hweight32(nv_rd32(dev, 0x002204));
NV_DEBUG(dev, "PFIFO: %d subfifo(s)\n", priv->spoon_nr);
/* assign engines to subfifos */ /* assign engines to subfifos */
nv_wr32(dev, 0x002208, ~(1 << 0)); /* PGRAPH */ if (priv->spoon_nr >= 3) {
nv_wr32(dev, 0x00220c, ~(1 << 1)); /* PVP */ nv_wr32(dev, 0x002208, ~(1 << 0)); /* PGRAPH */
nv_wr32(dev, 0x002210, ~(1 << 1)); /* PPP */ nv_wr32(dev, 0x00220c, ~(1 << 1)); /* PVP */
nv_wr32(dev, 0x002214, ~(1 << 1)); /* PBSP */ nv_wr32(dev, 0x002210, ~(1 << 1)); /* PPP */
nv_wr32(dev, 0x002218, ~(1 << 2)); /* PCE0 */ nv_wr32(dev, 0x002214, ~(1 << 1)); /* PBSP */
nv_wr32(dev, 0x00221c, ~(1 << 1)); /* PCE1 */ nv_wr32(dev, 0x002218, ~(1 << 2)); /* PCE0 */
nv_wr32(dev, 0x00221c, ~(1 << 1)); /* PCE1 */
}
/* PSUBFIFO[n] */ /* PSUBFIFO[n] */
for (i = 0; i < 3; i++) { for (i = 0; i < 3; i++) {