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drm/radeon: fix ordering in pll picking on dce4+

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No functional change, but re-order the cases so they
evaluate properly due to the way the DCE macros work.

Noticed by kallisti5 on IRC.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Deucher
2012-08-06 17:06:03 -04:00
parent 81ee8fb6b5
commit ecd67955fd
1 changed files with 4 additions and 4 deletions
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8
drivers/gpu/drm/radeon/atombios_crtc.c
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@@ -1531,12 +1531,12 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc)
* crtc virtual pixel clock. * crtc virtual pixel clock.
*/ */
if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_encoder))) { if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_encoder))) {
if (ASIC_IS_DCE5(rdev)) if (rdev->clock.dp_extclk)
return ATOM_DCPLL; return ATOM_PPLL_INVALID;
else if (ASIC_IS_DCE6(rdev)) else if (ASIC_IS_DCE6(rdev))
return ATOM_PPLL0; return ATOM_PPLL0;
else if (rdev->clock.dp_extclk) else if (ASIC_IS_DCE5(rdev))
return ATOM_PPLL_INVALID; return ATOM_DCPLL;
} }
} }
} }