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Documentation, ABI: Update L3 cache index disable text

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Change contact person to AMD kernel mailing list, update text and
external references, drop "Users:" tag.

Cc: Randy Dunlap <rdunlap@xenotime.net>
Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
Link: http://lkml.kernel.org/r/1305553188-21061-4-git-send-email-bp@amd64.org
Acked-by: Greg Kroah-Hartman <gregkh@suse.de>
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
This commit is contained in:
Borislav Petkov
2011-05-16 15:39:48 +02:00
committed by H. Peter Anvin
parent 42be450565
commit eecaaba5b2
1 changed files with 16 additions and 16 deletions
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32
Documentation/ABI/testing/sysfs-devices-system-cpu
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@@ -183,21 +183,21 @@ Description: Discover and change clock speed of CPUs
to learn how to control the knobs. to learn how to control the knobs.
What: /sys/devices/system/cpu/cpu*/cache/index*/cache_disable_X What: /sys/devices/system/cpu/cpu*/cache/index3/cache_disable_{0,1}
Date: August 2008 Date: August 2008
KernelVersion: 2.6.27 KernelVersion: 2.6.27
Contact: mark.langsdorf@amd.com Contact: discuss@x86-64.org
Description: These files exist in every cpu's cache index directories. Description: Disable L3 cache indices
There are currently 2 cache_disable_# files in each
directory. Reading from these files on a supported
processor will return that cache disable index value
for that processor and node. Writing to one of these
files will cause the specificed cache index to be disabled.
Currently, only AMD Family 10h Processors support cache index These files exist in every CPU's cache/index3 directory. Each
disable, and only for their L3 caches. See the BIOS and cache_disable_{0,1} file corresponds to one disable slot which
Kernel Developer's Guide at can be used to disable a cache index. Reading from these files
http://support.amd.com/us/Embedded_TechDocs/31116-Public-GH-BKDG_3-28_5-28-09.pdf on a processor with this functionality will return the currently
for formatting information and other details on the disabled index for that node. There is one L3 structure per
cache index disable. node, or per internal node on MCM machines. Writing a valid
Users: joachim.deguara@amd.com index to one of these files will cause the specificed cache
index to be disabled.
All AMD processors with L3 caches provide this functionality.
For details, see BKDGs at
http://developer.amd.com/documentation/guides/Pages/default.aspx