[PATCH] chelsio: add support for other 10G boards
Add support for other versions of the 10G Chelsio boards. This is basically a port of the vendor driver with the TOE features removed. Signed-off-by: Stephen Hemminger <shemminger@osdl.org> Signed-off-by: Jeff Garzik <jeff@garzik.org>
This commit is contained in:
Stephen Hemminger
committed by
Jeff Garzik
Jeff Garzik
parent
415294ecbb
commit
f1d3d38af7
@@ -43,6 +43,7 @@
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#include "gmac.h"
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#include "cphy.h"
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#include "sge.h"
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#include "tp.h"
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#include "espi.h"
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/**
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@@ -59,7 +60,7 @@
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* otherwise.
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*/
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static int t1_wait_op_done(adapter_t *adapter, int reg, u32 mask, int polarity,
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int attempts, int delay)
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int attempts, int delay)
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{
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while (1) {
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u32 val = readl(adapter->regs + reg) & mask;
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@@ -78,7 +79,7 @@ static int t1_wait_op_done(adapter_t *adapter, int reg, u32 mask, int polarity,
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/*
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* Write a register over the TPI interface (unlocked and locked versions).
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*/
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static int __t1_tpi_write(adapter_t *adapter, u32 addr, u32 value)
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int __t1_tpi_write(adapter_t *adapter, u32 addr, u32 value)
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{
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int tpi_busy;
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@@ -98,16 +99,16 @@ int t1_tpi_write(adapter_t *adapter, u32 addr, u32 value)
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{
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int ret;
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spin_lock(&(adapter)->tpi_lock);
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spin_lock(&adapter->tpi_lock);
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ret = __t1_tpi_write(adapter, addr, value);
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spin_unlock(&(adapter)->tpi_lock);
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spin_unlock(&adapter->tpi_lock);
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return ret;
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}
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/*
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* Read a register over the TPI interface (unlocked and locked versions).
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*/
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static int __t1_tpi_read(adapter_t *adapter, u32 addr, u32 *valp)
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int __t1_tpi_read(adapter_t *adapter, u32 addr, u32 *valp)
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{
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int tpi_busy;
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@@ -128,18 +129,26 @@ int t1_tpi_read(adapter_t *adapter, u32 addr, u32 *valp)
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{
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int ret;
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spin_lock(&(adapter)->tpi_lock);
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spin_lock(&adapter->tpi_lock);
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ret = __t1_tpi_read(adapter, addr, valp);
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spin_unlock(&(adapter)->tpi_lock);
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spin_unlock(&adapter->tpi_lock);
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return ret;
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}
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/*
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* Set a TPI parameter.
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*/
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static void t1_tpi_par(adapter_t *adapter, u32 value)
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{
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writel(V_TPIPAR(value), adapter->regs + A_TPI_PAR);
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}
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/*
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* Called when a port's link settings change to propagate the new values to the
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* associated PHY and MAC. After performing the common tasks it invokes an
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* OS-specific handler.
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*/
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/* static */ void link_changed(adapter_t *adapter, int port_id)
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void t1_link_changed(adapter_t *adapter, int port_id)
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{
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int link_ok, speed, duplex, fc;
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struct cphy *phy = adapter->port[port_id].phy;
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@@ -159,7 +168,7 @@ int t1_tpi_read(adapter_t *adapter, u32 addr, u32 *valp)
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mac->ops->set_speed_duplex_fc(mac, speed, duplex, fc);
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lc->fc = (unsigned char)fc;
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}
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t1_link_changed(adapter, port_id, link_ok, speed, duplex, fc);
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t1_link_negotiated(adapter, port_id, link_ok, speed, duplex, fc);
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}
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static int t1_pci_intr_handler(adapter_t *adapter)
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@@ -217,7 +226,7 @@ static int mi1_mdio_ext_read(adapter_t *adapter, int phy_addr, int mmd_addr,
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{
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u32 addr = V_MI1_REG_ADDR(mmd_addr) | V_MI1_PHY_ADDR(phy_addr);
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spin_lock(&(adapter)->tpi_lock);
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spin_lock(&adapter->tpi_lock);
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/* Write the address we want. */
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__t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_ADDR, addr);
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@@ -227,12 +236,13 @@ static int mi1_mdio_ext_read(adapter_t *adapter, int phy_addr, int mmd_addr,
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mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);
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/* Write the operation we want. */
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__t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_OP, MI1_OP_INDIRECT_READ);
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__t1_tpi_write(adapter,
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A_ELMER0_PORT0_MI1_OP, MI1_OP_INDIRECT_READ);
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mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);
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/* Read the data. */
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__t1_tpi_read(adapter, A_ELMER0_PORT0_MI1_DATA, valp);
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spin_unlock(&(adapter)->tpi_lock);
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spin_unlock(&adapter->tpi_lock);
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return 0;
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}
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@@ -241,7 +251,7 @@ static int mi1_mdio_ext_write(adapter_t *adapter, int phy_addr, int mmd_addr,
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{
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u32 addr = V_MI1_REG_ADDR(mmd_addr) | V_MI1_PHY_ADDR(phy_addr);
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spin_lock(&(adapter)->tpi_lock);
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spin_lock(&adapter->tpi_lock);
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/* Write the address we want. */
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__t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_ADDR, addr);
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@@ -254,7 +264,7 @@ static int mi1_mdio_ext_write(adapter_t *adapter, int phy_addr, int mmd_addr,
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__t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_DATA, val);
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__t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_OP, MI1_OP_INDIRECT_WRITE);
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mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);
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spin_unlock(&(adapter)->tpi_lock);
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spin_unlock(&adapter->tpi_lock);
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return 0;
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}
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@@ -265,12 +275,25 @@ static struct mdio_ops mi1_mdio_ext_ops = {
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};
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enum {
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CH_BRD_T110_1CU,
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CH_BRD_N110_1F,
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CH_BRD_N210_1F,
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CH_BRD_T210_1F,
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CH_BRD_T210_1CU,
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CH_BRD_N204_4CU,
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};
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static struct board_info t1_board[] = {
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{ CHBT_BOARD_CHT110, 1/*ports#*/,
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SUPPORTED_10000baseT_Full /*caps*/, CHBT_TERM_T1,
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CHBT_MAC_PM3393, CHBT_PHY_MY3126,
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125000000/*clk-core*/, 150000000/*clk-mc3*/, 125000000/*clk-mc4*/,
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1/*espi-ports*/, 0/*clk-cspi*/, 44/*clk-elmer0*/, 1/*mdien*/,
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1/*mdiinv*/, 1/*mdc*/, 1/*phybaseaddr*/, &t1_pm3393_ops,
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&t1_my3126_ops, &mi1_mdio_ext_ops,
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"Chelsio T110 1x10GBase-CX4 TOE" },
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{ CHBT_BOARD_N110, 1/*ports#*/,
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SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE /*caps*/, CHBT_TERM_T1,
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CHBT_MAC_PM3393, CHBT_PHY_88X2010,
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@@ -289,12 +312,36 @@ static struct board_info t1_board[] = {
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&t1_mv88x201x_ops, &mi1_mdio_ext_ops,
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"Chelsio N210 1x10GBaseX NIC" },
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{ CHBT_BOARD_CHT210, 1/*ports#*/,
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SUPPORTED_10000baseT_Full /*caps*/, CHBT_TERM_T2,
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CHBT_MAC_PM3393, CHBT_PHY_88X2010,
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125000000/*clk-core*/, 133000000/*clk-mc3*/, 125000000/*clk-mc4*/,
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1/*espi-ports*/, 0/*clk-cspi*/, 44/*clk-elmer0*/, 0/*mdien*/,
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0/*mdiinv*/, 1/*mdc*/, 0/*phybaseaddr*/, &t1_pm3393_ops,
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&t1_mv88x201x_ops, &mi1_mdio_ext_ops,
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"Chelsio T210 1x10GBaseX TOE" },
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{ CHBT_BOARD_CHT210, 1/*ports#*/,
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SUPPORTED_10000baseT_Full /*caps*/, CHBT_TERM_T2,
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CHBT_MAC_PM3393, CHBT_PHY_MY3126,
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125000000/*clk-core*/, 133000000/*clk-mc3*/, 125000000/*clk-mc4*/,
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1/*espi-ports*/, 0/*clk-cspi*/, 44/*clk-elmer0*/, 1/*mdien*/,
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1/*mdiinv*/, 1/*mdc*/, 1/*phybaseaddr*/, &t1_pm3393_ops,
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&t1_my3126_ops, &mi1_mdio_ext_ops,
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"Chelsio T210 1x10GBase-CX4 TOE" },
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};
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struct pci_device_id t1_pci_tbl[] = {
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CH_DEVICE(8, 0, CH_BRD_T110_1CU),
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CH_DEVICE(8, 1, CH_BRD_T110_1CU),
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CH_DEVICE(7, 0, CH_BRD_N110_1F),
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CH_DEVICE(10, 1, CH_BRD_N210_1F),
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{ 0, }
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CH_DEVICE(11, 1, CH_BRD_T210_1F),
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CH_DEVICE(14, 1, CH_BRD_T210_1CU),
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CH_DEVICE(16, 1, CH_BRD_N204_4CU),
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{ 0 }
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};
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MODULE_DEVICE_TABLE(pci, t1_pci_tbl);
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@@ -390,9 +437,14 @@ int t1_link_start(struct cphy *phy, struct cmac *mac, struct link_config *lc)
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if (lc->supported & SUPPORTED_Autoneg) {
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lc->advertising &= ~(ADVERTISED_ASYM_PAUSE | ADVERTISED_PAUSE);
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if (fc) {
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lc->advertising |= ADVERTISED_ASYM_PAUSE;
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if (fc == (PAUSE_RX | PAUSE_TX))
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if (fc == ((PAUSE_RX | PAUSE_TX) &
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(mac->adapter->params.nports < 2)))
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lc->advertising |= ADVERTISED_PAUSE;
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else {
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lc->advertising |= ADVERTISED_ASYM_PAUSE;
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if (fc == PAUSE_RX)
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lc->advertising |= ADVERTISED_PAUSE;
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}
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}
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phy->ops->advertise(phy, lc->advertising);
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@@ -403,11 +455,15 @@ int t1_link_start(struct cphy *phy, struct cmac *mac, struct link_config *lc)
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mac->ops->set_speed_duplex_fc(mac, lc->speed,
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lc->duplex, fc);
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/* Also disables autoneg */
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phy->state = PHY_AUTONEG_RDY;
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phy->ops->set_speed_duplex(phy, lc->speed, lc->duplex);
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phy->ops->reset(phy, 0);
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} else
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} else {
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phy->state = PHY_AUTONEG_EN;
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phy->ops->autoneg_enable(phy); /* also resets PHY */
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}
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} else {
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phy->state = PHY_AUTONEG_RDY;
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mac->ops->set_speed_duplex_fc(mac, -1, -1, fc);
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lc->fc = (unsigned char)fc;
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phy->ops->reset(phy, 0);
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@@ -418,7 +474,7 @@ int t1_link_start(struct cphy *phy, struct cmac *mac, struct link_config *lc)
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/*
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* External interrupt handler for boards using elmer0.
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*/
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int elmer0_ext_intr_handler(adapter_t *adapter)
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int t1_elmer0_ext_intr_handler(adapter_t *adapter)
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{
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struct cphy *phy;
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int phy_cause;
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@@ -427,15 +483,34 @@ int elmer0_ext_intr_handler(adapter_t *adapter)
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t1_tpi_read(adapter, A_ELMER0_INT_CAUSE, &cause);
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switch (board_info(adapter)->board) {
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case CHBT_BOARD_CHT210:
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case CHBT_BOARD_N210:
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case CHBT_BOARD_N110:
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if (cause & ELMER0_GP_BIT6) { /* Marvell 88x2010 interrupt */
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phy = adapter->port[0].phy;
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phy_cause = phy->ops->interrupt_handler(phy);
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if (phy_cause & cphy_cause_link_change)
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link_changed(adapter, 0);
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t1_link_changed(adapter, 0);
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}
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break;
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case CHBT_BOARD_8000:
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case CHBT_BOARD_CHT110:
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CH_DBG(adapter, INTR, "External interrupt cause 0x%x\n",
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cause);
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if (cause & ELMER0_GP_BIT1) { /* PMC3393 INTB */
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struct cmac *mac = adapter->port[0].mac;
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mac->ops->interrupt_handler(mac);
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}
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if (cause & ELMER0_GP_BIT5) { /* XPAK MOD_DETECT */
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u32 mod_detect;
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t1_tpi_read(adapter,
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A_ELMER0_GPI_STAT, &mod_detect);
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CH_MSG(adapter, INFO, LINK, "XPAK %s\n",
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mod_detect ? "removed" : "inserted");
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}
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break;
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}
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t1_tpi_write(adapter, A_ELMER0_INT_CAUSE, cause);
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return 0;
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@@ -445,11 +520,11 @@ int elmer0_ext_intr_handler(adapter_t *adapter)
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void t1_interrupts_enable(adapter_t *adapter)
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{
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unsigned int i;
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u32 pl_intr;
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adapter->slow_intr_mask = F_PL_INTR_SGE_ERR;
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adapter->slow_intr_mask = F_PL_INTR_SGE_ERR | F_PL_INTR_TP;
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t1_sge_intr_enable(adapter->sge);
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t1_tp_intr_enable(adapter->tp);
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if (adapter->espi) {
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adapter->slow_intr_mask |= F_PL_INTR_ESPI;
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t1_espi_intr_enable(adapter->espi);
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@@ -462,15 +537,17 @@ void t1_interrupts_enable(adapter_t *adapter)
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}
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/* Enable PCIX & external chip interrupts on ASIC boards. */
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pl_intr = readl(adapter->regs + A_PL_ENABLE);
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if (t1_is_asic(adapter)) {
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u32 pl_intr = readl(adapter->regs + A_PL_ENABLE);
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/* PCI-X interrupts */
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pci_write_config_dword(adapter->pdev, A_PCICFG_INTR_ENABLE,
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0xffffffff);
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/* PCI-X interrupts */
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pci_write_config_dword(adapter->pdev, A_PCICFG_INTR_ENABLE,
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0xffffffff);
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adapter->slow_intr_mask |= F_PL_INTR_EXT | F_PL_INTR_PCIX;
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pl_intr |= F_PL_INTR_EXT | F_PL_INTR_PCIX;
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writel(pl_intr, adapter->regs + A_PL_ENABLE);
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adapter->slow_intr_mask |= F_PL_INTR_EXT | F_PL_INTR_PCIX;
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pl_intr |= F_PL_INTR_EXT | F_PL_INTR_PCIX;
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writel(pl_intr, adapter->regs + A_PL_ENABLE);
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}
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}
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/* Disables all interrupts. */
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@@ -479,6 +556,7 @@ void t1_interrupts_disable(adapter_t* adapter)
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unsigned int i;
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t1_sge_intr_disable(adapter->sge);
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t1_tp_intr_disable(adapter->tp);
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if (adapter->espi)
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t1_espi_intr_disable(adapter->espi);
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@@ -489,7 +567,8 @@ void t1_interrupts_disable(adapter_t* adapter)
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}
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/* Disable PCIX & external chip interrupts. */
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writel(0, adapter->regs + A_PL_ENABLE);
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if (t1_is_asic(adapter))
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writel(0, adapter->regs + A_PL_ENABLE);
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/* PCI-X interrupts */
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pci_write_config_dword(adapter->pdev, A_PCICFG_INTR_ENABLE, 0);
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@@ -501,10 +580,9 @@ void t1_interrupts_disable(adapter_t* adapter)
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void t1_interrupts_clear(adapter_t* adapter)
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{
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unsigned int i;
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u32 pl_intr;
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t1_sge_intr_clear(adapter->sge);
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t1_tp_intr_clear(adapter->tp);
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if (adapter->espi)
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t1_espi_intr_clear(adapter->espi);
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@@ -515,10 +593,12 @@ void t1_interrupts_clear(adapter_t* adapter)
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}
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/* Enable interrupts for external devices. */
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pl_intr = readl(adapter->regs + A_PL_CAUSE);
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if (t1_is_asic(adapter)) {
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u32 pl_intr = readl(adapter->regs + A_PL_CAUSE);
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writel(pl_intr | F_PL_INTR_EXT | F_PL_INTR_PCIX,
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adapter->regs + A_PL_CAUSE);
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writel(pl_intr | F_PL_INTR_EXT | F_PL_INTR_PCIX,
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adapter->regs + A_PL_CAUSE);
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}
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/* PCI-X interrupts */
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pci_write_config_dword(adapter->pdev, A_PCICFG_INTR_CAUSE, 0xffffffff);
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@@ -527,7 +607,7 @@ void t1_interrupts_clear(adapter_t* adapter)
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/*
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* Slow path interrupt handler for ASICs.
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*/
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int t1_slow_intr_handler(adapter_t *adapter)
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static int asic_slow_intr(adapter_t *adapter)
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{
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u32 cause = readl(adapter->regs + A_PL_CAUSE);
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@@ -536,89 +616,50 @@ int t1_slow_intr_handler(adapter_t *adapter)
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return 0;
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if (cause & F_PL_INTR_SGE_ERR)
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t1_sge_intr_error_handler(adapter->sge);
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if (cause & F_PL_INTR_TP)
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t1_tp_intr_handler(adapter->tp);
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if (cause & F_PL_INTR_ESPI)
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t1_espi_intr_handler(adapter->espi);
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if (cause & F_PL_INTR_PCIX)
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t1_pci_intr_handler(adapter);
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if (cause & F_PL_INTR_EXT)
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t1_elmer0_ext_intr(adapter);
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t1_elmer0_ext_intr_handler(adapter);
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/* Clear the interrupts just processed. */
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writel(cause, adapter->regs + A_PL_CAUSE);
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(void)readl(adapter->regs + A_PL_CAUSE); /* flush writes */
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readl(adapter->regs + A_PL_CAUSE); /* flush writes */
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return 1;
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}
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/* Pause deadlock avoidance parameters */
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#define DROP_MSEC 16
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#define DROP_PKTS_CNT 1
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|
||||
static void set_csum_offload(adapter_t *adapter, u32 csum_bit, int enable)
|
||||
int t1_slow_intr_handler(adapter_t *adapter)
|
||||
{
|
||||
u32 val = readl(adapter->regs + A_TP_GLOBAL_CONFIG);
|
||||
|
||||
if (enable)
|
||||
val |= csum_bit;
|
||||
else
|
||||
val &= ~csum_bit;
|
||||
writel(val, adapter->regs + A_TP_GLOBAL_CONFIG);
|
||||
return asic_slow_intr(adapter);
|
||||
}
|
||||
|
||||
void t1_tp_set_ip_checksum_offload(adapter_t *adapter, int enable)
|
||||
/* Power sequencing is a work-around for Intel's XPAKs. */
|
||||
static void power_sequence_xpak(adapter_t* adapter)
|
||||
{
|
||||
set_csum_offload(adapter, F_IP_CSUM, enable);
|
||||
}
|
||||
u32 mod_detect;
|
||||
u32 gpo;
|
||||
|
||||
void t1_tp_set_udp_checksum_offload(adapter_t *adapter, int enable)
|
||||
{
|
||||
set_csum_offload(adapter, F_UDP_CSUM, enable);
|
||||
}
|
||||
|
||||
void t1_tp_set_tcp_checksum_offload(adapter_t *adapter, int enable)
|
||||
{
|
||||
set_csum_offload(adapter, F_TCP_CSUM, enable);
|
||||
}
|
||||
|
||||
static void t1_tp_reset(adapter_t *adapter, unsigned int tp_clk)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
val = F_TP_IN_CSPI_CPL | F_TP_IN_CSPI_CHECK_IP_CSUM |
|
||||
F_TP_IN_CSPI_CHECK_TCP_CSUM | F_TP_IN_ESPI_ETHERNET;
|
||||
val |= F_TP_IN_ESPI_CHECK_IP_CSUM |
|
||||
F_TP_IN_ESPI_CHECK_TCP_CSUM;
|
||||
writel(val, adapter->regs + A_TP_IN_CONFIG);
|
||||
writel(F_TP_OUT_CSPI_CPL |
|
||||
F_TP_OUT_ESPI_ETHERNET |
|
||||
F_TP_OUT_ESPI_GENERATE_IP_CSUM |
|
||||
F_TP_OUT_ESPI_GENERATE_TCP_CSUM,
|
||||
adapter->regs + A_TP_OUT_CONFIG);
|
||||
|
||||
val = readl(adapter->regs + A_TP_GLOBAL_CONFIG);
|
||||
val &= ~(F_IP_CSUM | F_UDP_CSUM | F_TCP_CSUM);
|
||||
writel(val, adapter->regs + A_TP_GLOBAL_CONFIG);
|
||||
|
||||
/*
|
||||
* Enable pause frame deadlock prevention.
|
||||
*/
|
||||
if (is_T2(adapter)) {
|
||||
u32 drop_ticks = DROP_MSEC * (tp_clk / 1000);
|
||||
|
||||
writel(F_ENABLE_TX_DROP | F_ENABLE_TX_ERROR |
|
||||
V_DROP_TICKS_CNT(drop_ticks) |
|
||||
V_NUM_PKTS_DROPPED(DROP_PKTS_CNT),
|
||||
adapter->regs + A_TP_TX_DROP_CONFIG);
|
||||
/* Check for XPAK */
|
||||
t1_tpi_read(adapter, A_ELMER0_GPI_STAT, &mod_detect);
|
||||
if (!(ELMER0_GP_BIT5 & mod_detect)) {
|
||||
/* XPAK is present */
|
||||
t1_tpi_read(adapter, A_ELMER0_GPO, &gpo);
|
||||
gpo |= ELMER0_GP_BIT18;
|
||||
t1_tpi_write(adapter, A_ELMER0_GPO, gpo);
|
||||
}
|
||||
|
||||
writel(F_TP_RESET, adapter->regs + A_TP_RESET);
|
||||
}
|
||||
|
||||
int __devinit t1_get_board_rev(adapter_t *adapter, const struct board_info *bi,
|
||||
struct adapter_params *p)
|
||||
{
|
||||
p->chip_version = bi->chip_term;
|
||||
p->is_asic = (p->chip_version != CHBT_TERM_FPGA);
|
||||
if (p->chip_version == CHBT_TERM_T1 ||
|
||||
p->chip_version == CHBT_TERM_T2) {
|
||||
p->chip_version == CHBT_TERM_T2 ||
|
||||
p->chip_version == CHBT_TERM_FPGA) {
|
||||
u32 val = readl(adapter->regs + A_TP_PC_CONFIG);
|
||||
|
||||
val = G_TP_PC_REV(val);
|
||||
@@ -640,10 +681,22 @@ int __devinit t1_get_board_rev(adapter_t *adapter, const struct board_info *bi,
|
||||
static int board_init(adapter_t *adapter, const struct board_info *bi)
|
||||
{
|
||||
switch (bi->board) {
|
||||
case CHBT_BOARD_8000:
|
||||
case CHBT_BOARD_N110:
|
||||
case CHBT_BOARD_N210:
|
||||
writel(V_TPIPAR(0xf), adapter->regs + A_TPI_PAR);
|
||||
t1_tpi_write(adapter, A_ELMER0_GPO, 0x800);
|
||||
case CHBT_BOARD_CHT210:
|
||||
case CHBT_BOARD_COUGAR:
|
||||
t1_tpi_par(adapter, 0xf);
|
||||
t1_tpi_write(adapter, A_ELMER0_GPO, 0x800);
|
||||
break;
|
||||
case CHBT_BOARD_CHT110:
|
||||
t1_tpi_par(adapter, 0xf);
|
||||
t1_tpi_write(adapter, A_ELMER0_GPO, 0x1800);
|
||||
|
||||
/* TBD XXX Might not need. This fixes a problem
|
||||
* described in the Intel SR XPAK errata.
|
||||
*/
|
||||
power_sequence_xpak(adapter);
|
||||
break;
|
||||
}
|
||||
return 0;
|
||||
@@ -670,7 +723,8 @@ int t1_init_hw_modules(adapter_t *adapter)
|
||||
bi->espi_nports))
|
||||
goto out_err;
|
||||
|
||||
t1_tp_reset(adapter, bi->clock_core);
|
||||
if (t1_tp_reset(adapter->tp, &adapter->params.tp, bi->clock_core))
|
||||
goto out_err;
|
||||
|
||||
err = t1_sge_configure(adapter->sge, &adapter->params.sge);
|
||||
if (err)
|
||||
@@ -714,6 +768,8 @@ void t1_free_sw_modules(adapter_t *adapter)
|
||||
|
||||
if (adapter->sge)
|
||||
t1_sge_destroy(adapter->sge);
|
||||
if (adapter->tp)
|
||||
t1_tp_destroy(adapter->tp);
|
||||
if (adapter->espi)
|
||||
t1_espi_destroy(adapter->espi);
|
||||
}
|
||||
@@ -762,6 +818,13 @@ int __devinit t1_init_sw_modules(adapter_t *adapter,
|
||||
goto error;
|
||||
}
|
||||
|
||||
adapter->tp = t1_tp_create(adapter, &adapter->params.tp);
|
||||
if (!adapter->tp) {
|
||||
CH_ERR("%s: TP initialization failed\n",
|
||||
adapter->name);
|
||||
goto error;
|
||||
}
|
||||
|
||||
board_init(adapter, bi);
|
||||
bi->mdio_ops->init(adapter, bi);
|
||||
if (bi->gphy->reset)
|
||||
@@ -793,7 +856,9 @@ int __devinit t1_init_sw_modules(adapter_t *adapter,
|
||||
* Get the port's MAC addresses either from the EEPROM if one
|
||||
* exists or the one hardcoded in the MAC.
|
||||
*/
|
||||
if (vpd_macaddress_get(adapter, i, hw_addr)) {
|
||||
if (!t1_is_asic(adapter) || bi->chip_mac == CHBT_MAC_DUMMY)
|
||||
mac->ops->macaddress_get(mac, hw_addr);
|
||||
else if (vpd_macaddress_get(adapter, i, hw_addr)) {
|
||||
CH_ERR("%s: could not read MAC address from VPD ROM\n",
|
||||
adapter->port[i].dev->name);
|
||||
goto error;
|
||||
@@ -806,7 +871,7 @@ int __devinit t1_init_sw_modules(adapter_t *adapter,
|
||||
t1_interrupts_clear(adapter);
|
||||
return 0;
|
||||
|
||||
error:
|
||||
error:
|
||||
t1_free_sw_modules(adapter);
|
||||
return -1;
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user