perf_events, x86: Split PMU definitions into separate files
Split amd,p6,intel into separate files so that we can easily deal with CONFIG_CPU_SUP_* things, needed to make things build now that perf_event.c relies on symbols from amd.c Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> LKML-Reference: <new-submission> Signed-off-by: Ingo Molnar <mingo@elte.hu>
This commit is contained in:
Peter Zijlstra
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Ingo Molnar
Ingo Molnar
parent
48fb4fdd6b
commit
f22f54f449
157
arch/x86/kernel/cpu/perf_event_p6.c
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157
arch/x86/kernel/cpu/perf_event_p6.c
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#ifdef CONFIG_CPU_SUP_INTEL
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/*
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* Not sure about some of these
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*/
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static const u64 p6_perfmon_event_map[] =
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{
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[PERF_COUNT_HW_CPU_CYCLES] = 0x0079,
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[PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
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[PERF_COUNT_HW_CACHE_REFERENCES] = 0x0f2e,
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[PERF_COUNT_HW_CACHE_MISSES] = 0x012e,
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[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4,
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[PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5,
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[PERF_COUNT_HW_BUS_CYCLES] = 0x0062,
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};
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static u64 p6_pmu_event_map(int hw_event)
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{
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return p6_perfmon_event_map[hw_event];
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}
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/*
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* Event setting that is specified not to count anything.
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* We use this to effectively disable a counter.
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*
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* L2_RQSTS with 0 MESI unit mask.
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*/
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#define P6_NOP_EVENT 0x0000002EULL
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static u64 p6_pmu_raw_event(u64 hw_event)
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{
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#define P6_EVNTSEL_EVENT_MASK 0x000000FFULL
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#define P6_EVNTSEL_UNIT_MASK 0x0000FF00ULL
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#define P6_EVNTSEL_EDGE_MASK 0x00040000ULL
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#define P6_EVNTSEL_INV_MASK 0x00800000ULL
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#define P6_EVNTSEL_REG_MASK 0xFF000000ULL
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#define P6_EVNTSEL_MASK \
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(P6_EVNTSEL_EVENT_MASK | \
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P6_EVNTSEL_UNIT_MASK | \
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P6_EVNTSEL_EDGE_MASK | \
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P6_EVNTSEL_INV_MASK | \
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P6_EVNTSEL_REG_MASK)
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return hw_event & P6_EVNTSEL_MASK;
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}
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static struct event_constraint p6_event_constraints[] =
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{
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INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FLOPS */
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INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */
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INTEL_EVENT_CONSTRAINT(0x11, 0x1), /* FP_ASSIST */
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INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
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INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
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INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
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EVENT_CONSTRAINT_END
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};
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static void p6_pmu_disable_all(void)
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{
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u64 val;
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/* p6 only has one enable register */
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rdmsrl(MSR_P6_EVNTSEL0, val);
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val &= ~ARCH_PERFMON_EVENTSEL0_ENABLE;
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wrmsrl(MSR_P6_EVNTSEL0, val);
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}
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static void p6_pmu_enable_all(void)
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{
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unsigned long val;
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/* p6 only has one enable register */
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rdmsrl(MSR_P6_EVNTSEL0, val);
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val |= ARCH_PERFMON_EVENTSEL0_ENABLE;
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wrmsrl(MSR_P6_EVNTSEL0, val);
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}
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static inline void
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p6_pmu_disable_event(struct hw_perf_event *hwc, int idx)
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{
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struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
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u64 val = P6_NOP_EVENT;
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if (cpuc->enabled)
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val |= ARCH_PERFMON_EVENTSEL0_ENABLE;
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(void)checking_wrmsrl(hwc->config_base + idx, val);
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}
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static void p6_pmu_enable_event(struct hw_perf_event *hwc, int idx)
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{
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struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
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u64 val;
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val = hwc->config;
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if (cpuc->enabled)
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val |= ARCH_PERFMON_EVENTSEL0_ENABLE;
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(void)checking_wrmsrl(hwc->config_base + idx, val);
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}
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static __initconst struct x86_pmu p6_pmu = {
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.name = "p6",
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.handle_irq = x86_pmu_handle_irq,
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.disable_all = p6_pmu_disable_all,
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.enable_all = p6_pmu_enable_all,
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.enable = p6_pmu_enable_event,
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.disable = p6_pmu_disable_event,
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.eventsel = MSR_P6_EVNTSEL0,
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.perfctr = MSR_P6_PERFCTR0,
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.event_map = p6_pmu_event_map,
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.raw_event = p6_pmu_raw_event,
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.max_events = ARRAY_SIZE(p6_perfmon_event_map),
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.apic = 1,
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.max_period = (1ULL << 31) - 1,
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.version = 0,
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.num_events = 2,
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/*
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* Events have 40 bits implemented. However they are designed such
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* that bits [32-39] are sign extensions of bit 31. As such the
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* effective width of a event for P6-like PMU is 32 bits only.
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*
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* See IA-32 Intel Architecture Software developer manual Vol 3B
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*/
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.event_bits = 32,
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.event_mask = (1ULL << 32) - 1,
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.get_event_constraints = x86_get_event_constraints,
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.event_constraints = p6_event_constraints,
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};
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static __init int p6_pmu_init(void)
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{
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switch (boot_cpu_data.x86_model) {
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case 1:
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case 3: /* Pentium Pro */
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case 5:
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case 6: /* Pentium II */
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case 7:
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case 8:
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case 11: /* Pentium III */
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case 9:
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case 13:
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/* Pentium M */
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break;
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default:
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pr_cont("unsupported p6 CPU model %d ",
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boot_cpu_data.x86_model);
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return -ENODEV;
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}
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x86_pmu = p6_pmu;
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return 0;
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}
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#endif /* CONFIG_CPU_SUP_INTEL */
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