ARM: OMAP: USB: Change omap USB code to use omap_read/write instead of __REG
Change omap USB code to use omap_read/write instead of __REG for multi-omap Cc: David Brownell <david-b@pacbell.net> Cc: linux-usb@vger.kernel.org Cc: i2c@lm-sensors.org Signed-off-by: Tony Lindgren <tony@atomide.com>
This commit is contained in:
Tony Lindgren
@ -8,23 +8,22 @@
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/*
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* USB device/endpoint management registers
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*/
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#define UDC_REG(offset) __REG16(UDC_BASE + (offset))
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#define UDC_REV_REG UDC_REG(0x0) /* Revision */
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#define UDC_EP_NUM_REG UDC_REG(0x4) /* Which endpoint */
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#define UDC_REV (UDC_BASE + 0x0) /* Revision */
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#define UDC_EP_NUM (UDC_BASE + 0x4) /* Which endpoint */
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# define UDC_SETUP_SEL (1 << 6)
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# define UDC_EP_SEL (1 << 5)
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# define UDC_EP_DIR (1 << 4)
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/* low 4 bits for endpoint number */
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#define UDC_DATA_REG UDC_REG(0x08) /* Endpoint FIFO */
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#define UDC_CTRL_REG UDC_REG(0x0C) /* Endpoint control */
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#define UDC_DATA (UDC_BASE + 0x08) /* Endpoint FIFO */
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#define UDC_CTRL (UDC_BASE + 0x0C) /* Endpoint control */
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# define UDC_CLR_HALT (1 << 7)
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# define UDC_SET_HALT (1 << 6)
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# define UDC_CLRDATA_TOGGLE (1 << 3)
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# define UDC_SET_FIFO_EN (1 << 2)
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# define UDC_CLR_EP (1 << 1)
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# define UDC_RESET_EP (1 << 0)
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#define UDC_STAT_FLG_REG UDC_REG(0x10) /* Endpoint status */
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#define UDC_STAT_FLG (UDC_BASE + 0x10) /* Endpoint status */
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# define UDC_NO_RXPACKET (1 << 15)
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# define UDC_MISS_IN (1 << 14)
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# define UDC_DATA_FLUSH (1 << 13)
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@ -38,8 +37,8 @@
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# define UDC_FIFO_EN (1 << 2)
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# define UDC_NON_ISO_FIFO_EMPTY (1 << 1)
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# define UDC_NON_ISO_FIFO_FULL (1 << 0)
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#define UDC_RXFSTAT_REG UDC_REG(0x14) /* OUT bytecount */
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#define UDC_SYSCON1_REG UDC_REG(0x18) /* System config 1 */
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#define UDC_RXFSTAT (UDC_BASE + 0x14) /* OUT bytecount */
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#define UDC_SYSCON1 (UDC_BASE + 0x18) /* System config 1 */
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# define UDC_CFG_LOCK (1 << 8)
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# define UDC_DATA_ENDIAN (1 << 7)
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# define UDC_DMA_ENDIAN (1 << 6)
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@ -48,12 +47,12 @@
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# define UDC_SELF_PWR (1 << 2)
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# define UDC_SOFF_DIS (1 << 1)
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# define UDC_PULLUP_EN (1 << 0)
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#define UDC_SYSCON2_REG UDC_REG(0x1C) /* System config 2 */
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#define UDC_SYSCON2 (UDC_BASE + 0x1C) /* System config 2 */
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# define UDC_RMT_WKP (1 << 6)
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# define UDC_STALL_CMD (1 << 5)
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# define UDC_DEV_CFG (1 << 3)
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# define UDC_CLR_CFG (1 << 2)
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#define UDC_DEVSTAT_REG UDC_REG(0x20) /* Device status */
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#define UDC_DEVSTAT (UDC_BASE + 0x20) /* Device status */
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# define UDC_B_HNP_ENABLE (1 << 9)
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# define UDC_A_HNP_SUPPORT (1 << 8)
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# define UDC_A_ALT_HNP_SUPPORT (1 << 7)
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@ -64,26 +63,26 @@
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# define UDC_ADD (1 << 2)
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# define UDC_DEF (1 << 1)
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# define UDC_ATT (1 << 0)
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#define UDC_SOF_REG UDC_REG(0x24) /* Start of frame */
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#define UDC_SOF (UDC_BASE + 0x24) /* Start of frame */
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# define UDC_FT_LOCK (1 << 12)
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# define UDC_TS_OK (1 << 11)
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# define UDC_TS 0x03ff
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#define UDC_IRQ_EN_REG UDC_REG(0x28) /* Interrupt enable */
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#define UDC_IRQ_EN (UDC_BASE + 0x28) /* Interrupt enable */
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# define UDC_SOF_IE (1 << 7)
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# define UDC_EPN_RX_IE (1 << 5)
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# define UDC_EPN_TX_IE (1 << 4)
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# define UDC_DS_CHG_IE (1 << 3)
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# define UDC_EP0_IE (1 << 0)
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#define UDC_DMA_IRQ_EN_REG UDC_REG(0x2C) /* DMA irq enable */
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#define UDC_DMA_IRQ_EN (UDC_BASE + 0x2C) /* DMA irq enable */
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/* rx/tx dma channels numbered 1-3 not 0-2 */
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# define UDC_TX_DONE_IE(n) (1 << (4 * (n) - 2))
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# define UDC_RX_CNT_IE(n) (1 << (4 * (n) - 3))
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# define UDC_RX_EOT_IE(n) (1 << (4 * (n) - 4))
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#define UDC_IRQ_SRC_REG UDC_REG(0x30) /* Interrupt source */
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#define UDC_IRQ_SRC (UDC_BASE + 0x30) /* Interrupt source */
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# define UDC_TXN_DONE (1 << 10)
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# define UDC_RXN_CNT (1 << 9)
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# define UDC_RXN_EOT (1 << 8)
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# define UDC_SOF (1 << 7)
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# define UDC_IRQ_SOF (1 << 7)
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# define UDC_EPN_RX (1 << 5)
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# define UDC_EPN_TX (1 << 4)
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# define UDC_DS_CHG (1 << 3)
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@ -91,41 +90,41 @@
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# define UDC_EP0_RX (1 << 1)
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# define UDC_EP0_TX (1 << 0)
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# define UDC_IRQ_SRC_MASK 0x7bf
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#define UDC_EPN_STAT_REG UDC_REG(0x34) /* EP irq status */
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#define UDC_DMAN_STAT_REG UDC_REG(0x38) /* DMA irq status */
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#define UDC_EPN_STAT (UDC_BASE + 0x34) /* EP irq status */
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#define UDC_DMAN_STAT (UDC_BASE + 0x38) /* DMA irq status */
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# define UDC_DMA_RX_SB (1 << 12)
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# define UDC_DMA_RX_SRC(x) (((x)>>8) & 0xf)
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# define UDC_DMA_TX_SRC(x) (((x)>>0) & 0xf)
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/* DMA configuration registers: up to three channels in each direction. */
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#define UDC_RXDMA_CFG_REG UDC_REG(0x40) /* 3 eps for RX DMA */
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#define UDC_RXDMA_CFG (UDC_BASE + 0x40) /* 3 eps for RX DMA */
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# define UDC_DMA_REQ (1 << 12)
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#define UDC_TXDMA_CFG_REG UDC_REG(0x44) /* 3 eps for TX DMA */
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#define UDC_DATA_DMA_REG UDC_REG(0x48) /* rx/tx fifo addr */
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#define UDC_TXDMA_CFG (UDC_BASE + 0x44) /* 3 eps for TX DMA */
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#define UDC_DATA_DMA (UDC_BASE + 0x48) /* rx/tx fifo addr */
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/* rx/tx dma control, numbering channels 1-3 not 0-2 */
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#define UDC_TXDMA_REG(chan) UDC_REG(0x50 - 4 + 4 * (chan))
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#define UDC_TXDMA(chan) (UDC_BASE + 0x50 - 4 + 4 * (chan))
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# define UDC_TXN_EOT (1 << 15) /* bytes vs packets */
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# define UDC_TXN_START (1 << 14) /* start transfer */
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# define UDC_TXN_TSC 0x03ff /* units in xfer */
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#define UDC_RXDMA_REG(chan) UDC_REG(0x60 - 4 + 4 * (chan))
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#define UDC_RXDMA(chan) (UDC_BASE + 0x60 - 4 + 4 * (chan))
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# define UDC_RXN_STOP (1 << 15) /* enable EOT irq */
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# define UDC_RXN_TC 0x00ff /* packets in xfer */
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/*
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* Endpoint configuration registers (used before CFG_LOCK is set)
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* UDC_EP_TX_REG(0) is unused
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* UDC_EP_TX(0) is unused
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*/
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#define UDC_EP_RX_REG(endpoint) UDC_REG(0x80 + (endpoint)*4)
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#define UDC_EP_RX(endpoint) (UDC_BASE + 0x80 + (endpoint)*4)
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# define UDC_EPN_RX_VALID (1 << 15)
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# define UDC_EPN_RX_DB (1 << 14)
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/* buffer size in bits 13, 12 */
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# define UDC_EPN_RX_ISO (1 << 11)
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/* buffer pointer in low 11 bits */
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#define UDC_EP_TX_REG(endpoint) UDC_REG(0xc0 + (endpoint)*4)
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/* same bitfields as in RX_REG */
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#define UDC_EP_TX(endpoint) (UDC_BASE + 0xc0 + (endpoint)*4)
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/* same bitfields as in RX */
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/*-------------------------------------------------------------------------*/
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@ -195,14 +194,14 @@ struct omap_udc {
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/*-------------------------------------------------------------------------*/
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#define MOD_CONF_CTRL_0_REG __REG32(MOD_CONF_CTRL_0)
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#define VBUS_W2FC_1510 (1 << 17) /* 0 gpio0, 1 dvdd2 pin */
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/* MOD_CONF_CTRL_0 */
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#define VBUS_W2FC_1510 (1 << 17) /* 0 gpio0, 1 dvdd2 pin */
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#define FUNC_MUX_CTRL_0_REG __REG32(FUNC_MUX_CTRL_0)
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/* FUNC_MUX_CTRL_0 */
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#define VBUS_CTRL_1510 (1 << 19) /* 1 connected (software) */
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#define VBUS_MODE_1510 (1 << 18) /* 0 hardware, 1 software */
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#define HMC_1510 ((MOD_CONF_CTRL_0_REG >> 1) & 0x3f)
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#define HMC_1610 (OTG_SYSCON_2_REG & 0x3f)
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#define HMC_1510 ((omap_readl(MOD_CONF_CTRL_0) >> 1) & 0x3f)
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#define HMC_1610 (omap_readl(OTG_SYSCON_2) & 0x3f)
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#define HMC (cpu_is_omap15xx() ? HMC_1510 : HMC_1610)
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