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x86, cacheinfo: Cleanup L3 cache index disable support

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Adaptions to the changes of the AMD northbridge caching code: instead
of a bool in each l3 struct, use a flag in amd_northbridges.flags to
indicate L3 cache index disable support; use a pointer to the whole
northbridge instead of the misc device in the l3 struct; simplify the
initialisation; dynamically generate sysfs attribute array.

Signed-off-by: Hans Rosenfeld <hans.rosenfeld@amd.com>
Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
This commit is contained in:
Hans Rosenfeld
2010-10-29 17:14:32 +02:00
committed by Borislav Petkov
parent 9653a5c76c
commit f658bcfb26
3 changed files with 74 additions and 84 deletions
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10
arch/x86/kernel/amd_nb.c
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@@ -68,6 +68,16 @@ int amd_cache_northbridges(void)
boot_cpu_data.x86 == 0x15)
amd_northbridges.flags |= AMD_NB_GART;
/*
* Some CPU families support L3 Cache Index Disable. There are some
* limitations because of E382 and E388 on family 0x10.
*/
if (boot_cpu_data.x86 == 0x10 &&
boot_cpu_data.x86_model >= 0x8 &&
(boot_cpu_data.x86_model > 0x9 ||
boot_cpu_data.x86_mask >= 0x1))
amd_northbridges.flags |= AMD_NB_L3_INDEX_DISABLE;
return 0;
}
EXPORT_SYMBOL_GPL(amd_cache_northbridges);