agp/intel: Fix cache control for Sandybridge
Sandybridge GTT has new cache control bits in PTE, which controls graphics page cache in LLC or LLC/MLC, so we need to extend the mask function to respect the new bits. And set cache control to always LLC only by default on Gen6. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Cc: stable@kernel.org Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Chris Wilson
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@ -34,6 +34,7 @@
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#include <linux/slab.h>
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#include <linux/swap.h>
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#include <linux/pci.h>
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#include <linux/intel-gtt.h>
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static uint32_t i915_gem_get_gtt_alignment(struct drm_gem_object *obj);
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static int i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj);
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