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[ARM] Separate VIC (vectored interrupt controller) support from Versatile

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Other machines may wish to make use of the VIC support code, so
move it to arch/arm/common.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Russell King
2006-01-13 21:30:48 +00:00
committed by Russell King
parent 5ff3fd2716
commit fa0fe48fcc
8 changed files with 151 additions and 77 deletions
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58
arch/arm/mach-versatile/core.c
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@ -35,6 +35,7 @@
#include <asm/leds.h>
#include <asm/hardware/arm_timer.h>
#include <asm/hardware/icst307.h>
#include <asm/hardware/vic.h>
#include <asm/mach/arch.h>
#include <asm/mach/flash.h>
@ -56,24 +57,6 @@
#define VA_VIC_BASE __io_address(VERSATILE_VIC_BASE)
#define VA_SIC_BASE __io_address(VERSATILE_SIC_BASE)
static void vic_mask_irq(unsigned int irq)
{
irq -= IRQ_VIC_START;
writel(1 << irq, VA_VIC_BASE + VIC_IRQ_ENABLE_CLEAR);
}
static void vic_unmask_irq(unsigned int irq)
{
irq -= IRQ_VIC_START;
writel(1 << irq, VA_VIC_BASE + VIC_IRQ_ENABLE);
}
static struct irqchip vic_chip = {
.ack = vic_mask_irq,
.mask = vic_mask_irq,
.unmask = vic_unmask_irq,
};
static void sic_mask_irq(unsigned int irq)
{
irq -= IRQ_SIC_START;
@ -127,43 +110,12 @@ sic_handle_irq(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs)
void __init versatile_init_irq(void)
{
unsigned int i, value;
unsigned int i;
/* Disable all interrupts initially. */
writel(0, VA_VIC_BASE + VIC_INT_SELECT);
writel(0, VA_VIC_BASE + VIC_IRQ_ENABLE);
writel(~0, VA_VIC_BASE + VIC_IRQ_ENABLE_CLEAR);
writel(0, VA_VIC_BASE + VIC_IRQ_STATUS);
writel(0, VA_VIC_BASE + VIC_ITCR);
writel(~0, VA_VIC_BASE + VIC_IRQ_SOFT_CLEAR);
/*
* Make sure we clear all existing interrupts
*/
writel(0, VA_VIC_BASE + VIC_VECT_ADDR);
for (i = 0; i < 19; i++) {
value = readl(VA_VIC_BASE + VIC_VECT_ADDR);
writel(value, VA_VIC_BASE + VIC_VECT_ADDR);
}
for (i = 0; i < 16; i++) {
value = readl(VA_VIC_BASE + VIC_VECT_CNTL0 + (i * 4));
writel(value | VICVectCntl_Enable | i, VA_VIC_BASE + VIC_VECT_CNTL0 + (i * 4));
}
writel(32, VA_VIC_BASE + VIC_DEF_VECT_ADDR);
for (i = IRQ_VIC_START; i <= IRQ_VIC_END; i++) {
if (i != IRQ_VICSOURCE31) {
set_irq_chip(i, &vic_chip);
set_irq_handler(i, do_level_IRQ);
set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
}
}
vic_init(VA_VIC_BASE, ~(1 << 31));
set_irq_handler(IRQ_VICSOURCE31, sic_handle_irq);
vic_unmask_irq(IRQ_VICSOURCE31);
enable_irq(IRQ_VICSOURCE31);
/* Do second interrupt controller */
writel(~0, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR);
@ -877,7 +829,7 @@ static unsigned long versatile_gettimeoffset(void)
ticks2 = readl(TIMER0_VA_BASE + TIMER_VALUE) & 0xffff;
do {
ticks1 = ticks2;
status = __raw_readl(VA_IC_BASE + VIC_IRQ_RAW_STATUS);
status = __raw_readl(VA_IC_BASE + VIC_RAW_STATUS);
ticks2 = readl(TIMER0_VA_BASE + TIMER_VALUE) & 0xffff;
} while (ticks2 > ticks1);