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powerpc/book3e: Add ICSWX/ACOP support to Book3e cores like A2

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ICSWX is also used by the A2 processor to access coprocessors,
although not all "chips" that contain A2s have coprocessors.

Signed-off-by: Jimi Xenidis <jimix@pobox.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
This commit is contained in:
Jimi Xenidis
2011-09-29 10:55:13 +00:00
committed by Benjamin Herrenschmidt
parent 9d67028090
commit fac26ad4f9
6 changed files with 19 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
arch/powerpc/include/asm/cputable.h
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@@ -437,7 +437,7 @@ extern const char *powerpc_base_platform;
#define CPU_FTRS_COMPATIBLE (CPU_FTR_USE_TB | CPU_FTR_PPCAS_ARCH_V2) #define CPU_FTRS_COMPATIBLE (CPU_FTR_USE_TB | CPU_FTR_PPCAS_ARCH_V2)
#define CPU_FTRS_A2 (CPU_FTR_USE_TB | CPU_FTR_SMT | CPU_FTR_DBELL | \ #define CPU_FTRS_A2 (CPU_FTR_USE_TB | CPU_FTR_SMT | CPU_FTR_DBELL | \
CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN) CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN | CPU_FTR_ICSWX)
#ifdef __powerpc64__ #ifdef __powerpc64__
#ifdef CONFIG_PPC_BOOK3E #ifdef CONFIG_PPC_BOOK3E

4
arch/powerpc/include/asm/mmu-book3e.h
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@@ -214,6 +214,10 @@ typedef struct {
unsigned int id; unsigned int id;
unsigned int active; unsigned int active;
unsigned long vdso_base; unsigned long vdso_base;
#ifdef CONFIG_PPC_ICSWX
struct spinlock *cop_lockp; /* guard cop related stuff */
unsigned long acop; /* mask of enabled coprocessor types */
#endif /* CONFIG_PPC_ICSWX */
#ifdef CONFIG_PPC_MM_SLICES #ifdef CONFIG_PPC_MM_SLICES
u64 low_slices_psize; /* SLB page size encodings */ u64 low_slices_psize; /* SLB page size encodings */
u64 high_slices_psize; /* 4 bits per slice for now */ u64 high_slices_psize; /* 4 bits per slice for now */

4
arch/powerpc/include/asm/reg_booke.h
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@@ -187,6 +187,10 @@
#define SPRN_CSRR1 SPRN_SRR3 /* Critical Save and Restore Register 1 */ #define SPRN_CSRR1 SPRN_SRR3 /* Critical Save and Restore Register 1 */
#endif #endif
#ifdef CONFIG_PPC_ICSWX
#define SPRN_HACOP 0x15F /* Hypervisor Available Coprocessor Register */
#endif
/* Bit definitions for CCR1. */ /* Bit definitions for CCR1. */
#define CCR1_DPC 0x00000100 /* Disable L1 I-Cache/D-Cache parity checking */ #define CCR1_DPC 0x00000100 /* Disable L1 I-Cache/D-Cache parity checking */
#define CCR1_TCS 0x00000080 /* Timer Clock Select */ #define CCR1_TCS 0x00000080 /* Timer Clock Select */

10
arch/powerpc/kernel/cpu_setup_a2.S
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@@ -41,11 +41,16 @@ _GLOBAL(__setup_cpu_a2)
* core local but doing it always won't hurt * core local but doing it always won't hurt
*/ */
#ifdef CONFIG_PPC_WSP_COPRO #ifdef CONFIG_PPC_ICSWX
/* Make sure ACOP starts out as zero */ /* Make sure ACOP starts out as zero */
li r3,0 li r3,0
mtspr SPRN_ACOP,r3 mtspr SPRN_ACOP,r3
/* Skip the following if we are in Guest mode */
mfmsr r3
andis. r0,r3,MSR_GS@h
bne _icswx_skip_guest
/* Enable icswx instruction */ /* Enable icswx instruction */
mfspr r3,SPRN_A2_CCR2 mfspr r3,SPRN_A2_CCR2
ori r3,r3,A2_CCR2_ENABLE_ICSWX ori r3,r3,A2_CCR2_ENABLE_ICSWX
@@ -54,7 +59,8 @@ _GLOBAL(__setup_cpu_a2)
/* Unmask all CTs in HACOP */ /* Unmask all CTs in HACOP */
li r3,-1 li r3,-1
mtspr SPRN_HACOP,r3 mtspr SPRN_HACOP,r3
#endif /* CONFIG_PPC_WSP_COPRO */ _icswx_skip_guest:
#endif /* CONFIG_PPC_ICSWX */
/* Enable doorbell */ /* Enable doorbell */
mfspr r3,SPRN_A2_CCR2 mfspr r3,SPRN_A2_CCR2

2
arch/powerpc/platforms/Kconfig.cputype
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@@ -236,7 +236,7 @@ config VSX
config PPC_ICSWX config PPC_ICSWX
bool "Support for PowerPC icswx coprocessor instruction" bool "Support for PowerPC icswx coprocessor instruction"
depends on POWER4 depends on POWER4 || PPC_A2
default n default n
---help--- ---help---

1
arch/powerpc/platforms/wsp/Kconfig
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@@ -1,6 +1,7 @@
config PPC_WSP config PPC_WSP
bool bool
select PPC_A2 select PPC_A2
select PPC_ICSWX
select PPC_SCOM select PPC_SCOM
select PPC_XICS select PPC_XICS
select PPC_ICP_NATIVE select PPC_ICP_NATIVE