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x86: coding style fixes to arch/x86/kernel/cpu/amd.c

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Before:
   total: 42 errors, 26 warnings, 350 lines checked
After:
   total: 0 errors, 26 warnings, 352 lines checked

No code changed:

arch/x86/kernel/cpu/amd.o:

   text	   data	    bss	    dec	    hex	filename
   1936	    328	      0	   2264	    8d8	amd.o.before
   1936	    328	      0	   2264	    8d8	amd.o.after

md5:
   873430a88faaf31bb4bbfe3a2a691e45  amd.o.before.asm
   873430a88faaf31bb4bbfe3a2a691e45  amd.o.after.asm

Signed-off-by: Paolo Ciarrocchi <paolo.ciarrocchi@gmail.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
This commit is contained in:
Paolo Ciarrocchi
2008-02-22 23:10:33 +01:00
committed by Ingo Molnar
parent f975182719
commit fb87a298fb
1 changed files with 48 additions and 46 deletions
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24
arch/x86/kernel/cpu/amd.c
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@@ -81,7 +81,8 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
#ifdef CONFIG_SMP #ifdef CONFIG_SMP
unsigned long long value; unsigned long long value;
/* Disable TLB flush filter by setting HWCR.FFDIS on K8 /*
* Disable TLB flush filter by setting HWCR.FFDIS on K8
* bit 6 of msr C001_0015 * bit 6 of msr C001_0015
* *
* Errata 63 for SH-B3 steppings * Errata 63 for SH-B3 steppings
@@ -102,14 +103,15 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
* no bus pipeline) * no bus pipeline)
*/ */
/* Bit 31 in normal CPUID used for nonstandard 3DNow ID; /*
3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */ * Bit 31 in normal CPUID used for nonstandard 3DNow ID;
* DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway
*/
clear_bit(0*32+31, c->x86_capability); clear_bit(0*32+31, c->x86_capability);
r = get_model_name(c); r = get_model_name(c);
switch(c->x86) switch (c->x86) {
{
case 4: case 4:
/* /*
* General Systems BIOSen alias the cpu frequency registers * General Systems BIOSen alias the cpu frequency registers
@@ -126,8 +128,7 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
} }
break; break;
case 5: case 5:
if( c->x86_model < 6 ) if (c->x86_model < 6) {
{
/* Based on AMD doc 20734R - June 2000 */ /* Based on AMD doc 20734R - June 2000 */
if (c->x86_model == 0) { if (c->x86_model == 0) {
clear_bit(X86_FEATURE_APIC, c->x86_capability); clear_bit(X86_FEATURE_APIC, c->x86_capability);
@@ -219,7 +220,8 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
break; break;
case 6: /* An Athlon/Duron */ case 6: /* An Athlon/Duron */
/* Bit 15 of Athlon specific MSR 15, needs to be 0 /*
* Bit 15 of Athlon specific MSR 15, needs to be 0
* to enable SSE on Palomino/Morgan/Barton CPU's. * to enable SSE on Palomino/Morgan/Barton CPU's.
* If the BIOS didn't enable it already, enable it here. * If the BIOS didn't enable it already, enable it here.
*/ */
@@ -233,7 +235,8 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
} }
} }
/* It's been determined by AMD that Athlons since model 8 stepping 1 /*
* It's been determined by AMD that Athlons since model 8 stepping 1
* are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx
* As per AMD technical note 27212 0.2 * As per AMD technical note 27212 0.2
*/ */
@@ -264,9 +267,8 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
display_cacheinfo(c); display_cacheinfo(c);
if (cpuid_eax(0x80000000) >= 0x80000008) { if (cpuid_eax(0x80000000) >= 0x80000008)
c->x86_max_cores = (cpuid_ecx(0x80000008) & 0xff) + 1; c->x86_max_cores = (cpuid_ecx(0x80000008) & 0xff) + 1;
}
#ifdef CONFIG_X86_HT #ifdef CONFIG_X86_HT
/* /*