i386: move pci
Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Ingo Molnar <mingo@elte.hu>
This commit is contained in:
Thomas Gleixner
315
arch/x86/pci/mmconfig-shared.c
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315
arch/x86/pci/mmconfig-shared.c
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/*
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* mmconfig-shared.c - Low-level direct PCI config space access via
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* MMCONFIG - common code between i386 and x86-64.
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*
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* This code does:
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* - known chipset handling
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* - ACPI decoding and validation
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*
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* Per-architecture code takes care of the mappings and accesses
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* themselves.
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*/
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/acpi.h>
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#include <linux/bitmap.h>
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#include <asm/e820.h>
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#include "pci.h"
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/* aperture is up to 256MB but BIOS may reserve less */
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#define MMCONFIG_APER_MIN (2 * 1024*1024)
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#define MMCONFIG_APER_MAX (256 * 1024*1024)
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DECLARE_BITMAP(pci_mmcfg_fallback_slots, 32*PCI_MMCFG_MAX_CHECK_BUS);
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/* Indicate if the mmcfg resources have been placed into the resource table. */
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static int __initdata pci_mmcfg_resources_inserted;
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/* K8 systems have some devices (typically in the builtin northbridge)
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that are only accessible using type1
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Normally this can be expressed in the MCFG by not listing them
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and assigning suitable _SEGs, but this isn't implemented in some BIOS.
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Instead try to discover all devices on bus 0 that are unreachable using MM
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and fallback for them. */
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static void __init unreachable_devices(void)
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{
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int i, bus;
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/* Use the max bus number from ACPI here? */
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for (bus = 0; bus < PCI_MMCFG_MAX_CHECK_BUS; bus++) {
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for (i = 0; i < 32; i++) {
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unsigned int devfn = PCI_DEVFN(i, 0);
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u32 val1, val2;
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pci_conf1_read(0, bus, devfn, 0, 4, &val1);
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if (val1 == 0xffffffff)
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continue;
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if (pci_mmcfg_arch_reachable(0, bus, devfn)) {
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raw_pci_ops->read(0, bus, devfn, 0, 4, &val2);
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if (val1 == val2)
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continue;
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}
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set_bit(i + 32 * bus, pci_mmcfg_fallback_slots);
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printk(KERN_NOTICE "PCI: No mmconfig possible on device"
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" %02x:%02x\n", bus, i);
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}
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}
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}
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static const char __init *pci_mmcfg_e7520(void)
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{
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u32 win;
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pci_conf1_read(0, 0, PCI_DEVFN(0,0), 0xce, 2, &win);
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win = win & 0xf000;
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if(win == 0x0000 || win == 0xf000)
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pci_mmcfg_config_num = 0;
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else {
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pci_mmcfg_config_num = 1;
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pci_mmcfg_config = kzalloc(sizeof(pci_mmcfg_config[0]), GFP_KERNEL);
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if (!pci_mmcfg_config)
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return NULL;
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pci_mmcfg_config[0].address = win << 16;
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pci_mmcfg_config[0].pci_segment = 0;
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pci_mmcfg_config[0].start_bus_number = 0;
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pci_mmcfg_config[0].end_bus_number = 255;
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}
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return "Intel Corporation E7520 Memory Controller Hub";
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}
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static const char __init *pci_mmcfg_intel_945(void)
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{
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u32 pciexbar, mask = 0, len = 0;
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pci_mmcfg_config_num = 1;
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pci_conf1_read(0, 0, PCI_DEVFN(0,0), 0x48, 4, &pciexbar);
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/* Enable bit */
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if (!(pciexbar & 1))
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pci_mmcfg_config_num = 0;
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/* Size bits */
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switch ((pciexbar >> 1) & 3) {
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case 0:
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mask = 0xf0000000U;
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len = 0x10000000U;
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break;
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case 1:
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mask = 0xf8000000U;
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len = 0x08000000U;
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break;
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case 2:
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mask = 0xfc000000U;
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len = 0x04000000U;
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break;
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default:
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pci_mmcfg_config_num = 0;
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}
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/* Errata #2, things break when not aligned on a 256Mb boundary */
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/* Can only happen in 64M/128M mode */
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if ((pciexbar & mask) & 0x0fffffffU)
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pci_mmcfg_config_num = 0;
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/* Don't hit the APIC registers and their friends */
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if ((pciexbar & mask) >= 0xf0000000U)
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pci_mmcfg_config_num = 0;
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if (pci_mmcfg_config_num) {
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pci_mmcfg_config = kzalloc(sizeof(pci_mmcfg_config[0]), GFP_KERNEL);
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if (!pci_mmcfg_config)
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return NULL;
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pci_mmcfg_config[0].address = pciexbar & mask;
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pci_mmcfg_config[0].pci_segment = 0;
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pci_mmcfg_config[0].start_bus_number = 0;
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pci_mmcfg_config[0].end_bus_number = (len >> 20) - 1;
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}
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return "Intel Corporation 945G/GZ/P/PL Express Memory Controller Hub";
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}
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struct pci_mmcfg_hostbridge_probe {
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u32 vendor;
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u32 device;
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const char *(*probe)(void);
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};
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static struct pci_mmcfg_hostbridge_probe pci_mmcfg_probes[] __initdata = {
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, pci_mmcfg_e7520 },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945G_HB, pci_mmcfg_intel_945 },
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};
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static int __init pci_mmcfg_check_hostbridge(void)
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{
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u32 l;
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u16 vendor, device;
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int i;
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const char *name;
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pci_conf1_read(0, 0, PCI_DEVFN(0,0), 0, 4, &l);
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vendor = l & 0xffff;
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device = (l >> 16) & 0xffff;
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pci_mmcfg_config_num = 0;
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pci_mmcfg_config = NULL;
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name = NULL;
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for (i = 0; !name && i < ARRAY_SIZE(pci_mmcfg_probes); i++) {
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if (pci_mmcfg_probes[i].vendor == vendor &&
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pci_mmcfg_probes[i].device == device)
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name = pci_mmcfg_probes[i].probe();
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}
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if (name) {
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printk(KERN_INFO "PCI: Found %s %s MMCONFIG support.\n",
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name, pci_mmcfg_config_num ? "with" : "without");
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}
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return name != NULL;
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}
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static void __init pci_mmcfg_insert_resources(unsigned long resource_flags)
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{
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#define PCI_MMCFG_RESOURCE_NAME_LEN 19
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int i;
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struct resource *res;
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char *names;
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unsigned num_buses;
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res = kcalloc(PCI_MMCFG_RESOURCE_NAME_LEN + sizeof(*res),
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pci_mmcfg_config_num, GFP_KERNEL);
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if (!res) {
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printk(KERN_ERR "PCI: Unable to allocate MMCONFIG resources\n");
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return;
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}
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names = (void *)&res[pci_mmcfg_config_num];
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for (i = 0; i < pci_mmcfg_config_num; i++, res++) {
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struct acpi_mcfg_allocation *cfg = &pci_mmcfg_config[i];
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num_buses = cfg->end_bus_number - cfg->start_bus_number + 1;
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res->name = names;
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snprintf(names, PCI_MMCFG_RESOURCE_NAME_LEN, "PCI MMCONFIG %u",
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cfg->pci_segment);
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res->start = cfg->address;
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res->end = res->start + (num_buses << 20) - 1;
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res->flags = IORESOURCE_MEM | resource_flags;
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insert_resource(&iomem_resource, res);
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names += PCI_MMCFG_RESOURCE_NAME_LEN;
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}
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/* Mark that the resources have been inserted. */
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pci_mmcfg_resources_inserted = 1;
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}
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static void __init pci_mmcfg_reject_broken(int type)
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{
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typeof(pci_mmcfg_config[0]) *cfg;
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if ((pci_mmcfg_config_num == 0) ||
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(pci_mmcfg_config == NULL) ||
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(pci_mmcfg_config[0].address == 0))
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return;
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cfg = &pci_mmcfg_config[0];
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/*
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* Handle more broken MCFG tables on Asus etc.
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* They only contain a single entry for bus 0-0.
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*/
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if (pci_mmcfg_config_num == 1 &&
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cfg->pci_segment == 0 &&
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(cfg->start_bus_number | cfg->end_bus_number) == 0) {
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printk(KERN_ERR "PCI: start and end of bus number is 0. "
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"Rejected as broken MCFG.\n");
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goto reject;
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}
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/*
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* Only do this check when type 1 works. If it doesn't work
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* assume we run on a Mac and always use MCFG
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*/
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if (type == 1 && !e820_all_mapped(cfg->address,
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cfg->address + MMCONFIG_APER_MIN,
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E820_RESERVED)) {
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printk(KERN_ERR "PCI: BIOS Bug: MCFG area at %Lx is not"
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" E820-reserved\n", cfg->address);
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goto reject;
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}
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return;
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reject:
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printk(KERN_ERR "PCI: Not using MMCONFIG.\n");
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kfree(pci_mmcfg_config);
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pci_mmcfg_config = NULL;
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pci_mmcfg_config_num = 0;
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}
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void __init pci_mmcfg_init(int type)
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{
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int known_bridge = 0;
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if ((pci_probe & PCI_PROBE_MMCONF) == 0)
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return;
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if (type == 1 && pci_mmcfg_check_hostbridge())
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known_bridge = 1;
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if (!known_bridge) {
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acpi_table_parse(ACPI_SIG_MCFG, acpi_parse_mcfg);
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pci_mmcfg_reject_broken(type);
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}
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if ((pci_mmcfg_config_num == 0) ||
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(pci_mmcfg_config == NULL) ||
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(pci_mmcfg_config[0].address == 0))
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return;
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if (pci_mmcfg_arch_init()) {
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if (type == 1)
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unreachable_devices();
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if (known_bridge)
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pci_mmcfg_insert_resources(IORESOURCE_BUSY);
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pci_probe = (pci_probe & ~PCI_PROBE_MASK) | PCI_PROBE_MMCONF;
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} else {
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/*
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* Signal not to attempt to insert mmcfg resources because
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* the architecture mmcfg setup could not initialize.
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*/
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pci_mmcfg_resources_inserted = 1;
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}
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}
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static int __init pci_mmcfg_late_insert_resources(void)
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{
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/*
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* If resources are already inserted or we are not using MMCONFIG,
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* don't insert the resources.
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*/
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if ((pci_mmcfg_resources_inserted == 1) ||
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(pci_probe & PCI_PROBE_MMCONF) == 0 ||
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(pci_mmcfg_config_num == 0) ||
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(pci_mmcfg_config == NULL) ||
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(pci_mmcfg_config[0].address == 0))
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return 1;
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/*
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* Attempt to insert the mmcfg resources but not with the busy flag
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* marked so it won't cause request errors when __request_region is
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* called.
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*/
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pci_mmcfg_insert_resources(0);
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return 0;
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}
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/*
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* Perform MMCONFIG resource insertion after PCI initialization to allow for
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* misprogrammed MCFG tables that state larger sizes but actually conflict
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* with other system resources.
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*/
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late_initcall(pci_mmcfg_late_insert_resources);
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