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drm: Fix ordering of bit fields in EDID structure leading huge vsync values.

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Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@linux.ie>
This commit is contained in:
Jesse Barnes
2009-02-23 15:36:41 -08:00
committed by Dave Airlie
parent c8766ac593
commit fe56cf45f9
1 changed files with 2 additions and 2 deletions
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4
include/drm/drm_edid.h
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@@ -58,10 +58,10 @@ struct detailed_pixel_timing {
u8 hsync_pulse_width_lo; u8 hsync_pulse_width_lo;
u8 vsync_pulse_width_lo:4; u8 vsync_pulse_width_lo:4;
u8 vsync_offset_lo:4; u8 vsync_offset_lo:4;
u8 hsync_pulse_width_hi:2;
u8 hsync_offset_hi:2;
u8 vsync_pulse_width_hi:2; u8 vsync_pulse_width_hi:2;
u8 vsync_offset_hi:2; u8 vsync_offset_hi:2;
u8 hsync_pulse_width_hi:2;
u8 hsync_offset_hi:2;
u8 width_mm_lo; u8 width_mm_lo;
u8 height_mm_lo; u8 height_mm_lo;
u8 height_mm_hi:4; u8 height_mm_hi:4;