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[MIPS] Separate performance counter interrupts

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Support for performance counter overflow interrupt that is on a separate
interrupt from the timer.

Signed-off-by: Chris Dearman <chris@mips.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Chris Dearman
2007-05-24 22:24:20 +01:00
committed by Ralf Baechle
parent b72c052622
commit ffe9ee4709
4 changed files with 136 additions and 47 deletions
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7
arch/mips/oprofile/op_model_mipsxx.c
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@ -177,7 +177,10 @@ static int mipsxx_perfcount_handler(void)
unsigned int counters = op_model_mipsxx_ops.num_counters;
unsigned int control;
unsigned int counter;
int handled = 0;
int handled = IRQ_NONE;
if (cpu_has_mips_r2 && !(read_c0_cause() & (1 << 26)))
return handled;
switch (counters) {
#define HANDLE_COUNTER(n) \
@ -188,7 +191,7 @@ static int mipsxx_perfcount_handler(void)
(counter & M_COUNTER_OVERFLOW)) { \
oprofile_add_sample(get_irq_regs(), n); \
w_c0_perfcntr ## n(reg.counter[n]); \
handled = 1; \
handled = IRQ_HANDLED; \
}
HANDLE_COUNTER(3)
HANDLE_COUNTER(2)