Commit Graph

1557 Commits

Author SHA1 Message Date
Russell King
314e47b7b6 ARM: l2c: print a warning with L2C-310 caches if the cache size is modified
As we have now removed all instances of the L2C-310 having its cache
size "modified" via platform/SoC code, discourage new cases showing
up by printing a warning.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-30 00:50:37 +01:00
Russell King
678ea28b7c ARM: l2c: remove old .set_debug method
We no longer need or require the .set_debug method; we handle everything
it used to do via the .write_sec method instead.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-30 00:50:35 +01:00
Russell King
de7e75326c ARM: l2c: provide common PL310 early resume code
Provide a common assembly implementation for PL310 resume code.  Certain
platforms need to re-initialise the L2C cache early as it may preserve
data across a S2RAM cycle, and therefore must be enabled along with the
L1 cache and MMU.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-30 00:49:01 +01:00
Russell King
a4b041a0e2 ARM: l2c: always enable non-secure access to lockdown registers
Since we always write to these during the cache initialisation, it is
a good idea to always have the non-secure access bit set.  Set it in
core code.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-30 00:48:57 +01:00
Russell King
3a43b581da ARM: l2c: always enable low power modes
Always enable the L2C low power modes on L2C-310 R3P0 and newer parts.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-30 00:48:54 +01:00
Russell King
4374d64933 ARM: l2c: add automatic enable of early BRESP
The AXI bus protocol requires that a write response should only be
sent back to the master when the last write has been accepted.  Early
BRESP allows the L2C-310 to send the write response as soon as the
store buffer accepts the write address.

Cortex-A9 processors can signal to the L2C-310 that they wish to be
notified early, and if this optimisation is enabled, the L2C-310 can
signal an early write response.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-30 00:48:50 +01:00
Russell King
ddf7d79bc7 ARM: l2c: move L2 cache register saving to a more sensible location
Move the L2 cache register saving to a more sensible location - after
the cache has been enabled, and fixups have been run.  We move the
saving of the auxiliary control register into the ->save function as
well which makes everything operate in a sane and maintainable way.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-30 00:48:47 +01:00
Russell King
d9d1f3e2d7 ARM: l2c: check that DT files specify the required "cache-unified" property
This is a required property, and should always be specified.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-30 00:48:45 +01:00
Russell King
1a5a954ce0 ARM: l2c: fix register naming
We have a mixture of different devices with different register layouts,
but we group all the bits together in an opaque mess.  Split them out
into those which are L2C-310 specific and ones which refer to earlier
devices.  Provide full auxiliary control register definitions.

Acked-by: Tony Lindgren <tony@atomide.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-30 00:48:43 +01:00
Russell King
a8875a092a ARM: l2c: implement L2C-310 erratum 752271 in core L2C code
Rather than having SoCs work around L2C erratum themselves, move them
into core code.  This erratum affects the double linefill feature which
needs to be disabled for r3p0 to r3p1-50rel0.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-30 00:48:41 +01:00
Russell King
8abd259f65 ARM: l2c: provide generic hook to intercept writes to secure registers
When Linux is running in the non-secure world, any write to a secure
L2C register will generate an abort.  Platforms normally have to call
firmware to work around this.  Provide a hook for them to intercept
any L2C secure register write.

l2c_write_sec() avoids writes to secure registers which are already set
to the appropriate value, thus avoiding the overhead of needlessly
calling into the secure monitor.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-30 00:48:39 +01:00
Russell King
c0fe18ba30 ARM: l2c: move errata configuration options to arch/arm/mm/Kconfig
Move the L2C-310 errata configuration options to arch/arm/mm/Kconfig
along side the option which enables support for this device.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-30 00:48:37 +01:00
Russell King
0493aef4da ARM: l2c: move way size calculation data into l2c_init_data
Move the way size calculation data (base of way size) out of the
switch statement into the provided initialisation data.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-30 00:48:34 +01:00
Russell King
5f47c38704 ARM: l2c: add decode for L2C-220 cache ways
Rather than assuming these are always 8-way, it can be decoded from the
auxillary register in the same manner as L2C-210.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-30 00:48:33 +01:00
Russell King
051334bdc5 ARM: l2c: move type string into l2c_init_data structure
Rather than decoding this from the ID register, store it in the
l2c_init_data structure.  This simplifies things some more, and
allows us to better provide further details as to how we're
driving the cache.  We print the cache ID value anyway should we
need to precisely identify the cache hardware.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-30 00:48:30 +01:00
Russell King
cf9ea8f130 ARM: l2c: remove obsolete l2x0 ops for non-OF init
non-OF initialisation has never been used with any cache controller
which isn't an ARM cache controller, so we can safely get rid of the
old (and buggy) l2x0_*-based operations structure.

This is also the last reference to:
- l2x0_clean_line()
- l2x0_inv_line()
- l2x0_flush_line()
- l2x0_flush_all()
- l2x0_clean_all()
- l2x0_inv_all()
- l2x0_inv_range()
- l2x0_clean_range()
- l2x0_flush_range()
- l2x0_enable()
- l2x0_resume()
so kill those functions too.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-30 00:48:28 +01:00
Russell King
9081114837 ARM: l2c: convert Broadcom L2C-310 to new code
The Broadcom L2C-310 devices use ARMs L2C-310 R2P3 or later.  These
require no errata workarounds, and so we can directly call the l2c210
functions from their methods.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-30 00:48:26 +01:00
Russell King
733c6bbafd ARM: l2c: add L2C-220 specific handlers
The L2C-220 is different from the L2C-210 and L2C-310 in that every
operation is a background operation: this means we have to use
spinlocks to protect all operations, and we have to wait for every
operation to complete.

Should a second operation be attempted while a previous operation
is in progress, the response will be an imprecise abort.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-30 00:48:24 +01:00
Russell King
f777332ba7 ARM: l2c: use L2C-210 handlers for L2C-310 errata-less implementations
Where no errata affect the L2C-310 handlers, they are functionally
equivalent to L2C-210.  Re-use the L2C-210 handlers for the L2C-310
part.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-30 00:48:21 +01:00
Russell King
ebd4219f10 ARM: l2c: implement L2C-310 erratum 588369 as a method override
Implement L2C-310 erratum 588369 by overriding the invalidate range
and flush range methods in the outer_cache operations structure.
This allows us to sensibly contain the erratum code in one place
without affecting other locations/implemetations.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-30 00:48:19 +01:00
Russell King
99ca1772e5 ARM: l2c: implement L2C-310 erratum 727915 as a method override
Implement L2C-310 erratum 727915 by overriding the flush_all method
in the outer_cache operations structure.  This allows us to sensibly
contain the erratum code in one place without affecting other
locations or implementations.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-30 00:48:17 +01:00
Russell King
6a28cf59ff ARM: l2c: add L2C-210 specific handlers
Add L2C-210 specific cache operation handlers.  These are tailored to
the requirements of the L2C-210 cache controller, which doesn't
require any workarounds.  We avoid using the way operations during
normal operation, which means we can avoid locking: the only time
we use the way operations are during initialisation, and when
disabling the cache.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-30 00:48:15 +01:00
Russell King
bda0b74e6a ARM: l2c: move pl310_set_debug() into l2c-310 code
Move the pl310_set_debug() into the l2c-310 code area, and don't hide
it with ifdefs.  Rename it to l2c310_set_debug().

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-30 00:48:13 +01:00
Russell King
faf9b2e701 ARM: l2c: simplify l2x0 unlocking code
The l2x0 unlocking code is only called from l2x0_enable() now, so move
the logic entirely into that function and simplify it.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-30 00:48:11 +01:00
Russell King
09a5d180ed ARM: l2c: clean up save/resume functions
Rename the pl310 save/resume functions to have a l2c310 prefix - this
is it's official name.  Use a local cached copy of the l2x0_base
virtual address, and also realise that many of the resume function
tails are the same as the enable functions, so make a call to the
enable function instead of duplicating that code.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-30 00:48:08 +01:00
Russell King
b98556f26d ARM: l2c: move and add ARM L2C-2x0/L2C-310 save/resume code to non-OF
Add the save/resume code hooks to the non-OF implementations as well.
There's no reason for the non-OF implementations to be any different
from the OF implementations.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-30 00:48:05 +01:00
Russell King
cdef8689ef ARM: l2c: clean up L2 cache initialisation messages
Make one of them purely "English", and the other purely technical.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-30 00:48:03 +01:00
Russell King
75461f5c84 ARM: l2c: implement fixups for L2 cache controller quirks/errata
Rather than putting quirk handling in __l2c_init(), move it out to a
separate function which individual implementations can specify.  This
helps to localise the quirks to those implementations which require
them.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-30 00:48:01 +01:00
Russell King
40266d6f41 ARM: l2c: move aurora broadcast setup to enable function
Rather than having this hacked into the OF initialiation function, we
can handle this via the enable function instead.  While here, clean
up that code and comments a little.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-30 00:47:59 +01:00
Russell King
9a07f27bc5 ARM: l2c: only write the auxiliary control register if required
Avoid unnecessary writes to the auxiliary control register if the
register already contains the required value.  This allows us to
avoid invoking the platforms secure monitor code unnecessarily.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-30 00:47:57 +01:00
Russell King
17f3f99fab ARM: l2c: write auxctrl register before unlocking
We should write the auxillary control register before unlocking: the
write may be necessary to enable non-secure access to the lock
registers.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-30 00:47:54 +01:00
Russell King
3b8bad5758 ARM: l2c: provide enable method
Providing an enable method gives L2 cache controllers a chance to do
special handling at enable time.  This allows us to remove a hack in
l2x0_unlock() for Marvell Aurora L2 caches.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-30 00:47:51 +01:00
Russell King
da3627fbda ARM: l2c: group implementation specific code together
Back in the mists of time, someone decided that it would be a good idea
to group like functions together - so all the save functions in one
place, all the resume functions in another, all the OF parsing functions
some place else.

This makes it difficult to get an overview on what a particular
implementation is doing - grouping an implementations specific functions
together makes more sense, because you can see what it's doing without
the clutter of other implementations.

Organise it according to implementation.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-30 00:47:50 +01:00
Russell King
c40e7eb6c0 ARM: l2c: move l2c save function to __l2c_init()
There's no reason this functionality should be specific to DT, so move
it into the common initialisation function.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-30 00:47:47 +01:00
Russell King
9846dfc98f ARM: l2c: pass iomem address into data->save function
Pass the iomem address into this function so we don't have to keep
accessing it from a global.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-30 00:47:45 +01:00
Russell King
96054b0a99 ARM: l2c: clean up OF initialisation a bit
Rather than having a boolean and other tricks to disable some bits of
l2x0_init(), split this function into two parts: a common part shared
between OF and non-OF, and the non-OF part.

The common part can take a block of function pointers, and the cache
ID (to cope with Aurora's DT specified ID.)  Eliminate the redundant
setting of l2x0_base in the OF case, moving it to the non-OF init
function.

This allows us to localise the OF-specific initialisation handling
from the non-OF handling.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-30 00:47:43 +01:00
Russell King
14b882cfa3 ARM: l2c: add and use L2C revision constants
The revision namespace is specific to the L2 cache part, so don't name
these with generic identifiers, use a part specific identifier.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-30 00:47:41 +01:00
Russell King
83841fe1fb ARM: l2c: rename cache_wait_way()
cache_wait_way() is actually used to wait for a particular mask to
report clear; it's not really got much to do with cache ways at all.
Indeed, it gets used to wait for the C bit to clear on older caches.
Rename this with a more generic function name which better reflects
its purpose: l2c_wait_mask().

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-30 00:47:39 +01:00
Russell King
df5dd4c6e2 ARM: l2c: provide generic helper for way-based operations
Provide a generic helper function for way based operations.  These are
always background operations, and thus have to be waited for before a
new operation is commenced.  This helper extracts that requirement from
several locations in the code.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-30 00:47:36 +01:00
Russell King
37abcdb919 ARM: l2c: split out cache unlock code
Split the cache unlock code out of l2x0_unlock().  We want to be able
to re-use this functionality later.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-30 00:47:34 +01:00
Russell King
2b2a87a12d ARM: l2c: provide generic function for calling set_debug method
Provide a generic function which always calls the set_debug method.
This will be used later in the series as some work-arounds require
that the debug register be written.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-30 00:47:32 +01:00
Russell King
c02642bc10 ARM: l2c: rename OF specific things, making l2x0_of_data available to all
Rename a few things to help distinguish their function(s):
 l2x0_of_data -> l2c_init_data
 setup -> of_parse
 add of_ prefix to OF specific data

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-30 00:47:29 +01:00
Russell King
ce84130384 ARM: l2c: tidy up l2x0_of_data declarations
Remove NULL initialisers, make these all __initconst structures, and
order their members in the same order as the structure declaration.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-30 00:47:28 +01:00
Russell King
a65bb92560 ARM: l2c: add helper for L2 cache controller DT IDs
Make it easier to declare L2 cache controller DT IDs by using a macro.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-30 00:47:25 +01:00
Russell King
1f1d5b745a ARM: outer cache: add WARN_ON() to outer_disable()
Add WARN_ON() conditions to outer_disable() to ensure that its
requirements aren't violated.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-30 00:47:23 +01:00
Russell King
265c271c82 ARM: l2c: remove outer_inv_all() method
No one ever calls this function anywhere in the kernel, so let's
completely remove it from the outer cache API and turn it into an
internal-only thing.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-22 16:21:35 +01:00
Linus Torvalds
92891ed6b1 Merge branch 'fixes_for_v3.15' of git://git.linaro.org/people/mszyprowski/linux-dma-mapping
Pull dma-mapping fix from Marek Szyprowski:
 "A small fix for dma-mapping subsystem for ARM"

* 'fixes_for_v3.15' of git://git.linaro.org/people/mszyprowski/linux-dma-mapping:
  arm: dma-mapping: Fix mapping size value
2014-04-24 09:58:57 -07:00
Ritesh Harjani
59f0f119e8 arm: dma-mapping: Fix mapping size value
68efd7d2fb("arm: dma-mapping: remove order parameter from
arm_iommu_create_mapping()") is causing kernel panic
because it wrongly sets the value of mapping->size:

Unable to handle kernel NULL pointer dereference at virtual
address 000000a0
pgd = e7a84000
[000000a0] *pgd=00000000
...
PC is at bitmap_clear+0x48/0xd0
LR is at __iommu_remove_mapping+0x130/0x164

Fix it by correcting mapping->size value.

Signed-off-by: Ritesh Harjani <ritesh.harjani@gmail.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
2014-04-23 15:07:00 +02:00
Russell King
51aaf81fae ARM: keep arch/arm/Kconfig and arch/arm/mm/Kconfig select entries sorted
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-04-23 09:31:10 +01:00
Linus Torvalds
ede1d63fcc Merge branch 'for-linus' of git://ftp.arm.linux.org.uk/~rmk/linux-arm
Pull second set of ARM changes from Russell King:
 "This is the remainder of the ARM changes for this merge window.
  Included in this request are:

   - fixes for kprobes for big-endian support
   - fix tracing in soft_restart
   - avoid phys address overflow in kdump code
   - fix reporting of read-only pmd bits in kernel page table dump
   - remove unnecessary (and possibly buggy) call to outer_flush_all()
   - fix a three sparse warnings (missing header file for function
     prototypes)
   - fix pj4 crashing single zImage (thanks to arm-soc merging changes
     which enables this with knowledge that the corresponding fix had
     not even been submitted for my tree before the merge window opened)
   - vfp macro cleanups
   - dump register state on undefined instruction userspace faults when
     debugging"

* 'for-linus' of git://ftp.arm.linux.org.uk/~rmk/linux-arm:
  Dump the registers on undefined instruction userspace faults
  ARM: 8018/1: Add {inc,dec}_preempt_count asm macros
  ARM: 8017/1: Move asm macro get_thread_info to asm/assembler.h
  ARM: 8016/1: Check cpu id in pj4_cp0_init.
  ARM: 8015/1: Add cpu_is_pj4 to distinguish PJ4 because it has some differences with V7
  ARM: add missing system_misc.h include to process.c
  ARM: 8009/1: dcscb.c: remove call to outer_flush_all()
  ARM: 8014/1: mm: fix reporting of read-only PMD bits
  ARM: 8012/1: kdump: Avoid overflow when converting pfn to physaddr
  ARM: 8010/1: avoid tracers in soft_restart
  ARM: kprobes-test: Workaround GAS .align bug
  ARM: kprobes-test: use <asm/opcodes.h> for Thumb instruction building
  ARM: kprobes-test: use <asm/opcodes.h> for ARM instruction building
  ARM: kprobes-test: use <asm/opcodes.h> for instruction accesses
  ARM: probes: fix instruction fetch order with <asm/opcodes.h>
2014-04-11 11:56:40 -07:00