Commit Graph

24 Commits

Author SHA1 Message Date
Russell King
7921fc4a25 ARM: remove old RTC support
All RTC drivers have been converted to rtclib, so the old code
providing the set_rtc function pointer, save_time_delta() and
restore_time_delta() functions is obsolete.  Remove it.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2010-02-15 21:39:12 +00:00
Thomas Gleixner
239007b844 genirq: Convert irq_desc.lock to raw_spinlock
Convert locks which cannot be sleeping locks in preempt-rt to
raw_spinlocks.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Acked-by: Peter Zijlstra <peterz@infradead.org>
Acked-by: Ingo Molnar <mingo@elte.hu>
2009-12-14 23:55:33 +01:00
Linus Walleij
6ef297f86b ARM: 5720/1: Move MMCI header to amba include dir
This moves the mmci platform data definition struct away from
arch/arm/include/asm/mach/mmc.h into the more proper place among
the other primecells in include/linux/amba/mmci.h and at the same
time renames it to "mmci.h", and also the struct in this file
confusingly named mmc_platform_data has been renamed
mmci_platform_data for clarity.

Cc: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Linus Walleij <linus.walleij@stericsson.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-09-22 20:49:04 +01:00
Linus Walleij
9e6c82cd3e ARM: 5698/1: MMCI pass capabilities in platform data
This makes it possible to pass down the host controller
capabilities for the MMCI driver using the platform data. It
also provides the capabilties for the U300 implementation as an
example, and makes sure the 4bit wide mode is set if this is
requested by the ios() now that we can actually set that
capability for a platform.

Signed-off-by: Linus Walleij <linus.walleij@stericsson.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-09-15 22:11:06 +01:00
Russell King
7fb2bbf4d9 MMC: MMCI: allow GPIOs to be passed
Add and initialize the gpio_wp and gpio_cd members.  We need to
ensure that all users are covered, because GPIO 0 may be valid.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Acked-by: Linus Walleij <linus.walleij@stericsson.com>
2009-07-09 15:15:12 +01:00
Hiroshi DOYU
69d3a84a64 omap iommu: simple virtual address space management
This patch provides a device drivers, which has a omap iommu, with
address mapping APIs between device virtual address(iommu), physical
address and MPU virtual address.

There are 4 possible patterns for iommu virtual address(iova/da) mapping.

    |iova/			  mapping		iommu_		page
    | da	pa	va	(d)-(p)-(v)		function	type
  ---------------------------------------------------------------------------
  1 | c		c	c	 1 - 1 - 1	  _kmap() / _kunmap()	s
  2 | c		c,a	c	 1 - 1 - 1	_kmalloc()/ _kfree()	s
  3 | c		d	c	 1 - n - 1	  _vmap() / _vunmap()	s
  4 | c		d,a	c	 1 - n - 1	_vmalloc()/ _vfree()	n*

    'iova':	device iommu virtual address
    'da':	alias of 'iova'
    'pa':	physical address
    'va':	mpu virtual address

    'c':	contiguous memory area
    'd':	dicontiguous memory area
    'a':	anonymous memory allocation
    '()':	optional feature

    'n':	a normal page(4KB) size is used.
    's':	multiple iommu superpage(16MB, 1MB, 64KB, 4KB) size is used.

    '*':	not yet, but feasible.

Signed-off-by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
2009-05-19 08:23:49 +03:00
Paul Walmsley
e4707dd3e9 [ARM] 5422/1: ARM: MMU: add a Non-cacheable Normal executable memory type
This patch adds a Non-cacheable Normal ARM executable memory type,
MT_MEMORY_NONCACHED.

On OMAP3, this is used for rapid dynamic voltage/frequency scaling in
the VDD2 voltage domain. OMAP3's SDRAM controller (SDRC) is in the
VDD2 voltage domain, and its clock frequency must change along with
voltage. The SDRC clock change code cannot run from SDRAM itself,
since SDRAM accesses are paused during the clock change. So the
current implementation of the DVFS code executes from OMAP on-chip
SRAM, aka "OCM RAM."

If the OCM RAM pages are marked as Cacheable, the ARM cache controller
will attempt to flush dirty cache lines to the SDRC, so it can fill
those lines with OCM RAM instruction code. The problem is that the
SDRC is paused during DVFS, and so any SDRAM access causes the ARM MPU
subsystem to hang.

TI's original solution to this problem was to mark the OCM RAM
sections as Strongly Ordered memory, thus preventing caching. This is
overkill: since the memory is marked as non-bufferable, OCM RAM writes
become needlessly slow. The idea of "Strongly Ordered SRAM" is also
conceptually disturbing. Previous LAKML list discussion is here:

http://www.spinics.net/lists/arm-kernel/msg54312.html

This memory type MT_MEMORY_NONCACHED is used for OCM RAM by a future
patch.

Cc: Richard Woodruff <r-woodruff2@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-03-12 19:25:02 +00:00
Russell King
22b61a11fd Merge branch 'dma' into devel
Conflicts:

	arch/arm/plat-mxc/dma-mx1-mx2.c
2009-02-21 21:42:50 +00:00
Russell King
308d333ad6 [ARM] dma: move IOMD and floppy DMA structures to RiscPC DMA code
There's no point these being in a generic include file when they're
only used in arch/arm/mach-rpc/dma.c.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-02-21 21:36:22 +00:00
Bjorn Helgaas
06df69932a PCI: arm: use generic INTx swizzle from PCI core
Use the generic pci_common_swizzle() instead of arch-specific code.

Signed-off-by: Bjorn Helgaas <bjorn.helgaas@hp.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2009-01-07 11:13:13 -08:00
Russell King
f0ffc81625 [ARM] dma: remove dmamode_t typedef
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-01-02 12:34:55 +00:00
Russell King
8c56afcbea [ARM] dma: constify dma controller name and dma ops
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-12-11 14:52:42 +00:00
Russell King
ad9dd94c38 [ARM] dma: move RiscPC specific DMA data out of dma_struct
Separate the RiscPC specific (IOMD and floppy FIQ) data out of the core
DMA structure by making the IOMD and floppy DMA supersets.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-12-11 14:35:57 +00:00
Russell King
2f757f2ab7 [ARM] dma: rejig DMA initialization
Rather than having the central DMA multiplexer call the architecture
specific DMA initialization function, have each architecture DMA
initialization function use core_initcall(), and register each DMA
channel separately with the multiplexer.

This removes the array of dma structures in the central multiplexer,
replacing it with an array of pointers instead; this is more flexible
since it allows the drivers to wrap the DMA structure (eventually
allowing us to transition non-ISA DMA drivers away.)

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-12-11 14:32:43 +00:00
Russell King
1df8130278 [ARM] dma: remove dmach_t typedef
Remove a pointless integer typedef.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-12-08 15:58:50 +00:00
Russell King
ebb4c65869 [ARM] iop: iop3xx needs registers mapped uncached+unbuffered
Mikael Pettersson reported:

   The 2.6.28-rc kernels fail to detect PCI device 0000:00:01.0
   (the first ethernet port) on my Thecus n2100 XScale box.

   There is however still a strange "ghost" device that gets partially
   detected in 2.6.28-rc2 vanilla.

The IOP321 manual says:

  The user designates the memory region containing the OCCDR as
  non-cacheable and non-bufferable from the IntelR XScaleTM core.
  This guarantees that all load/stores to the OCCDR are only of
  DWORD quantities.

Ensure that the OCCDR is so mapped.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-11-09 11:18:36 +00:00
Russell King
3f30a09a61 Merge branch 'pxa-all' into devel
Conflicts:

	arch/arm/mach-pxa/Kconfig
	arch/arm/mach-pxa/corgi.c
	arch/arm/mach-pxa/include/mach/hardware.h
	arch/arm/mach-pxa/spitz.c
2008-10-09 21:33:02 +01:00
Russell King
5a89770daa Merge branches 'pxa-core' and 'pxa-machines' into pxa-all
Conflicts:

	arch/arm/mach-pxa/Kconfig
	arch/arm/mach-pxa/pxa25x.c
	arch/arm/mach-pxa/pxa27x.c
2008-10-07 19:08:56 +01:00
Russell King
9b727abdff [ARM] Remove MT_NONSHARED_DEVICE alias
Use MT_DEVICE_NONSHARED instead.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-10-01 16:41:07 +01:00
Russell King
db5b716947 [ARM] Remove MT_DEVICE_IXP2000 and associated definitions
As of the previous commit, MT_DEVICE_IXP2000 encodes to the same
PTE bit encoding as MT_DEVICE, so it's now redundant.  Convert
MT_DEVICE_IXP2000 to use MT_DEVICE instead, and remove its aliases.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-10-01 16:41:06 +01:00
Russell King
73b610affe [ARM] pxa: remove references to pxa_gpio_mode() in comments
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-09-25 13:35:27 +01:00
Lennert Buytenhek
1ad77a876d [ARM] 5241/1: provide ioremap_wc()
This patch provides an ARM implementation of ioremap_wc().

We use different page table attributes depending on which CPU we
are running on:

- Non-XScale ARMv5 and earlier systems: The ARMv5 ARM documents four
  possible mapping types (CB=00/01/10/11).  We can't use any of the
  cached memory types (CB=10/11), since that breaks coherency with
  peripheral devices.  Both CB=00 and CB=01 are suitable for _wc, and
  CB=01 (Uncached/Buffered) allows the hardware more freedom than
  CB=00, so we'll use that.

  (The ARMv5 ARM seems to suggest that CB=01 is allowed to delay stores
  but isn't allowed to merge them, but there is no other mapping type
  we can use that allows the hardware to delay and merge stores, so
  we'll go with CB=01.)

- XScale v1/v2 (ARMv5): same as the ARMv5 case above, with the slight
  difference that on these platforms, CB=01 actually _does_ allow
  merging stores.  (If you want noncoalescing bufferable behavior
  on Xscale v1/v2, you need to use XCB=101.)

- Xscale v3 (ARMv5) and ARMv6+: on these systems, we use TEXCB=00100
  mappings (Inner/Outer Uncacheable in xsc3 parlance, Uncached Normal
  in ARMv6 parlance).

  The ARMv6 ARM explicitly says that any accesses to Normal memory can
  be merged, which makes Normal memory more suitable for _wc mappings
  than Device or Strongly Ordered memory, as the latter two mapping
  types are guaranteed to maintain transaction number, size and order.
  We use the Uncached variety of Normal mappings for the same reason
  that we can't use C=1 mappings on ARMv5.

  The xsc3 Architecture Specification documents TEXCB=00100 as being
  Uncacheable and allowing coalescing of writes, which is also just
  what we need.

Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-09-06 13:13:44 +01:00
Russell King
897d85275d [ARM] Fix circular include dependency with IRQ headers
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-08-07 09:39:37 +01:00
Russell King
4baa992243 [ARM] move include/asm-arm to arch/arm/include/asm
Move platform independent header files to arch/arm/include/asm, leaving
those in asm/arch* and asm/plat* alone.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-08-02 21:32:35 +01:00