Commit Graph

21586 Commits

Author SHA1 Message Date
David S. Miller
3cab0c3e86 [SPARC64]: More SUN4V cpu mondo bug fixing.
This cpu mondo sending interface isn't all that easy to
use correctly...

We were clearing out the wrong bits from the "mask" after getting
something other than EOK from the hypervisor.

It turns out the hypervisor can just be resent the same cpu_list[]
array, with the 0xffff "done" entries still in there, and it will do
the right thing.

So don't update or try to rebuild the cpu_list[] array to condense it.

This requires the "forward_progress" check to be done slightly
differently, but this new scheme is less bug prone than what we were
doing before.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:14:17 -08:00
David S. Miller
bcc28ee0bf [SPARC64]: Fix sun4v mna winfixup handling.
We were clobbering a base register before we were done
using it.  Fix a comment typo while we're here.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:14:16 -08:00
David S. Miller
c4f8ef77f9 [SPARC64]: Fix mini RTC driver reading.
Need to subtract 1900 from year and 1 from month before
giving it back to userspace.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:14:15 -08:00
David S. Miller
8bcd174116 [SPARC64]: Do not allow mapping pages within 4GB of 64-bit VA hole.
The UltraSPARC T1 manual recommends this because the chip
could instruction prefetch into the VA hole, and this would
also make decoding  certain kinds of memory access traps
more difficult (because the chip sign extends certain pieces
of trap state).

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:14:14 -08:00
David S. Miller
45f791eb0f [SPARC64]: Fix _PAGE_EXEC handling.
First of all, use the known _PAGE_EXEC_{4U,4V} value instead
of loading _PAGE_EXEC from memory.  We either know which one
to use by context, or we can code patch the test.

Next, we need to check executability of a PTE in the generic
TSB miss handler.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:14:13 -08:00
David S. Miller
92daa77e9a [SPARC64]: Fix typo in SUN4V D-TLB miss handler.
Should put FAULT_CODE_DTLB into %g3 not FAULT_CODE_ITLB.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:14:12 -08:00
David S. Miller
e22990451a [SPARC64]: Kill bogus function externs in asm/pgtable.h
These are all implemented inline earlier in the file.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:14:11 -08:00
David S. Miller
8ba706a95b [SPARC64]: Add mini-RTC driver for Starfire and SUN4V.
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:14:10 -08:00
David S. Miller
b830ab665a [SPARC64]: Fix bugs in SUN4V cpu mondo dispatch.
There were several bugs in the SUN4V cpu mondo dispatch code.

In fact, if we ever got a EWOULDBLOCK or other error from
the hypervisor call, we'd potentially send a cpu mondo multiple
times to the same cpu and even worse we could loop until the
timeout resending the same mondo over and over to such cpus.

So let's bulletproof this thing as follows:

1) Implement cpu_mondo_send() and cpu_state() hypervisor calls
   in arch/sparc64/kernel/entry.S, add prototypes to asm/hypervisor.h

2) Don't build and update the cpulist using inline functions, this
   was causing the cpu mask to not get updated in the caller.

3) Disable interrupts during the entire mondo send, otherwise our
   cpu list and/or mondo block could get overwritten if we take
   an interrupt and do a cpu mondo send on the current cpu.

4) Check for all possible error return types from the cpu_mondo_send()
   hypervisor call.  In particular:

   HV_EOK) Our work is done, all cpus have received the mondo.
   HV_CPUERROR) One or more of the cpus in the cpu list we passed
                to the hypervisor are in error state.  Use cpu_state()
                calls over the entries in the cpu list to see which
		ones.  Record them in "error_mask" and report this
		after we are done sending the mondo to cpus which are
		not in error state.
   HV_EWOULDBLOCK) We need to keep trying.

   Any other error we consider fatal, we report the event and exit
   immediately.

5) We only timeout if forward progress is not made.  Forward progress
   is defined as having at least one cpu get the mondo successfully
   in a given cpu_mondo_send() call.  Otherwise we bump a counter
   and delay a little.  If the counter hits a limit, we signal an
   error and report the event.

Also, smp_call_function_mask() error handling reports the number
of cpus incorrectly.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:14:09 -08:00
David S. Miller
aac0aadf09 [SPARC64]: Fix bugs in SMP TLB context version expiration handling.
1) We must flush the TLB, duh.

2) Even if the sw context was seen to be valid, the local cpu's
   hw context can be out of date, so reload it unconditionally.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:14:08 -08:00
David S. Miller
6889331a12 [SPARC64]: Fix indexing into kpte_linear_bitmap.
Need to shift back up by 3 bits to get 8-byte entry
index.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:14:07 -08:00
David S. Miller
97c4b6f95a [SPARC64]: Use 13-bit context size always.
We no longer have the problems that require using the smaller
sizes.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:14:06 -08:00
David S. Miller
7a591cfe4e [SPARC64]: Avoid dcache-dirty page state management on sun4v.
It is totally wasted work, since we have no D-cache aliasing
issues on sun4v.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:14:06 -08:00
David S. Miller
2a3a5f5ddb [SPARC64]: Bulletproof hypervisor TLB flushing.
Check TLB flush hypervisor calls for errors and report them.

Pass HV_MMU_ALL always for now, we can add back the optimization
to avoid the I-TLB flush later.

Always explicitly page align the virtual address arguments.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:14:05 -08:00
David S. Miller
6cc80cfab8 [SPARC64]: Report mondo error correctly in hypervisor_xcall_deliver().
It's in "arg0" not "func".

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:14:04 -08:00
David S. Miller
3634476239 [SPARC64]: Niagara optimized XOR functions for RAID.
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:14:03 -08:00
Andrew Morton
c4e9249b19 [SPARC64]: Fix binfmt_aout32.c build.
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:14:02 -08:00
David S. Miller
77b838fa1e [SPARC64]: destroy_context() needs to disable interrupts.
get_new_mmu_context() can be invoked from interrupt context
now for the new SMP version wrap handling.

So disable interrupt while taking ctx_alloc_lock in destroy_context()
so we don't deadlock.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:14:01 -08:00
David S. Miller
a0663a79ad [SPARC64]: Fix TLB context allocation with SMT style shared TLBs.
The context allocation scheme we use depends upon there being a 1<-->1
mapping from cpu to physical TLB for correctness.  Chips like Niagara
break this assumption.

So what we do is notify all cpus with a cross call when the context
version number changes, and if necessary this makes them allocate
a valid context for the address space they are running at the time.

Stress tested with make -j1024, make -j2048, and make -j4096 kernel
builds on a 32-strand, 8 core, T2000 with 16GB of ram.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:14:00 -08:00
David S. Miller
074d82cf68 [SPARC64]: Put syscall tables after trap table.
Otherwise with too much stuff enabled in the kernel config
we can end up with an unaligned trap table.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:59 -08:00
David S. Miller
b2bef4424c [SPARC64]: Export _PAGE_E and _PAGE_CACHE to modules.
SBUS flash driver needs it.

Noticed by Fabbione.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:58 -08:00
David S. Miller
0f05da6d57 [SPARC64]: Fix %tstate ASI handling in start_thread{,32}()
Niagara helps us find a ancient bug in the sparc64 port :-)

The ASI_* values are plain constant defines, thus signed 32-bit
on sparc64.  To put shift this into the regs->tstate value we were
doing or'ing "(ASI_PNF << 24)" into there.

ASI_PNF is 0x82 and shifted left by 24 makes that topmost bit the
sign bit in a 32-bit value.  This would get sign extended to 64-bits
and thus corrupt the top-half of the reg->tstate value.

This never caused problems in pre-Niagara cpus because the only thing
up there were the condition code values.  But Niagara has the global
register level field, and this all 1's value is illegal there so
Niagara gives an illegal instruction trap due to this bug.

I'm pretty sure this bug is about as old as the sparc64 port itself.

This also points out that we weren't setting ASI_PNF for 32-bit tasks.
We should, so fix that while we're here.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:57 -08:00
David S. Miller
fc50492867 [SPARC64]: Drop %gl to 0 before re-enabling PSTATE_IE in rtrap
If we take a window fault, on SUN4V set %gl to zero before we
turn PSTATE_IE back on in %pstate.  Otherwise if we take an
interrupt we'll end up with corrupt register state.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:57 -08:00
David S. Miller
d7744a0950 [SPARC64]: Create a seperate kernel TSB for 4MB/256MB mappings.
It can map all of the linear kernel mappings with zero TSB hash
conflicts for systems with 16GB or less ram.  In such cases, on
SUN4V, once we load up this TSB the first time with all the
mappings, we never take a linear kernel mapping TLB miss ever
again, the hypervisor handles them all.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:56 -08:00
David S. Miller
9cc3a1ac9a [SPARC64]: Make use of Niagara 256MB PTEs for kernel mappings.
We use a bitmap, one bit for every 256MB of memory.  If the
bit is set we can use a 256MB PTE for linear mappings, else
we have to use a 4MB PTE.

SUN4V support is there, and we can very easily add support
for Panther cpu 256MB PTEs in the future.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:55 -08:00
David S. Miller
30c91d576e [SPARC64]: Use sun4v_cpu_idle() in cpu_idle() on SUN4V.
We have to turn off the "polling nrflag" bit when we sleep
the cpu like this, so that we'll get a cross-cpu interrupt
to wake the processor up from the yield.

We also have to disable PSTATE_IE in %pstate around the yield
call and recheck need_resched() in order to avoid any races.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:54 -08:00
David S. Miller
689126a48a [SPARC64] math-emu: Delete debugging printk left by previous commit.
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:53 -08:00
David S. Miller
6f5374c91f [SPARC64]: Add sun4v_cpu_yield().
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:52 -08:00
David S. Miller
1bd0cd74d1 [SPARC64]: Kill cpudata->idle_volume.
Set, but never used.

We used to use this for dynamic IRQ retargetting, but that
code died a long time ago.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:51 -08:00
David S. Miller
8ca2557c48 [SPARC64]: Niagara optimized memset/bzero/clear_user.
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:50 -08:00
David S. Miller
d371c0c174 [SPARC64]: Pass multiple CPUs at once to hypervisor cross-call API.
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:49 -08:00
David S. Miller
c79f76777d [SPARC64]: Args to SUNW,set-trap-table are 64-bit.
They were getting truncated to 32-bit and this is very bad
when your MMU fault status area is in physical memory above
4GB on SUN4V.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:48 -08:00
David S. Miller
4e74ae800b [SPARC64]: Handle unimplemented FPU square-root on Niagara.
The math-emu code only expects unfinished fpop traps when
emulating FPU sqrt instructions on pre-Niagara chips.
On Niagara we can get unimplemented fpop, so handle that.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:48 -08:00
David S. Miller
f5deb807b8 [SPARC] serial: Make sure sysfs nodes get named correctly.
Because we play this trick where we use ttyS? in increasing minor
numbers for different sunfoo.c drivers, we have to inform the TTY
layer of this.

Do so by setting the tty->name_base appropriately.

Probably there should be a generic way to do this in the serial core,
but for now...

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:47 -08:00
David S. Miller
55555633bd [SPARC64]: Typo in sun4v_data_access_exception log message.
Should be "Dax" not "Iax".

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:46 -08:00
David S. Miller
d82965c167 [SPARC64]: Handle zero-length map requests in pci_sun4v.c
By simply changing the do-while loop into a plain
while loop.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:45 -08:00
David S. Miller
abf3b7bd89 [SPARC64]: Kill stray PGLIST_NENTS check in pci_sun4v.c
I forgot to remove the one in pci_4v_map_sg() during the
iommu batching commit.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:44 -08:00
David S. Miller
39334a4b2c [SPARC64]: Fix typo in dump_tl1_traplog()
Actually make use of the 'limit' we compute.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:43 -08:00
David S. Miller
37133c006c [SPARC64]: Disable smp_report_regs() for now.
It's extremely noisy and causes much grief on slow
consoles with large numbers of cpus.

We'll have to provide this some saner way in order
to re-enable this.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:42 -08:00
David S. Miller
6a32fd4d0d [SPARC64]: Remove PGLIST_NENTS PCI IOMMU mapping limitation on SUN4V.
Use a batching queue system for IOMMU mapping setup,
with a page sized batch.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:41 -08:00
David S. Miller
04d74758eb [SPARC64]: Use KERN_EMERG in dump_tl1_traplog() and sun4v TLB errors.
We're about to seriously die in these cases so it is important
that the messages make it to the console.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:40 -08:00
David S. Miller
24c523ecc6 [SPARC64]: Fix unaligned access winfxup handling on SUN4V.
Another case where we have to force ourselves into global register
level one.  Also make sure the arguments passed to sun4v_do_mna() are
correct.

This area actually needs some more work, for example spill fixup is
not necessarily going to do the right thing for this case.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:39 -08:00
David S. Miller
6cc200db95 [SPARC64]: Set %gl to 1 in kvmap_itlb_longpath on SUN4V.
Just like kvmap_dtlb_longpath we have to force the
global register level to one in order to mimick the
PSTATE_MG --> PSTATE_AG trasition done on SUN4U.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:39 -08:00
David S. Miller
843dfb4d99 [SPARC64] sunhv: Fix locking in sunhv_start_tx()
Caller takes the lock already.

Also, fixup the poll loop in sunhv_break_ctl().  Just
like in console write, we udelay(2) and use a loop
limit of 1000000 iterations.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:38 -08:00
David S. Miller
11fc04e46a [SPARC64]: Put sunhv.o earliest in the list of sparc serial drivers.
So that it will show up as /dev/ttyS0.  Otherwise things like
installers will try to run on whatever serial port gets probed
first.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:37 -08:00
David S. Miller
0f15952ac8 [SPARC64]: Export a PAGE_SHARED symbol.
For drivers/media/*, noticed by Fabbione.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:36 -08:00
Fabio M. Di Nitto
f6c1fe5292 [SPARC64] Fix build if CONFIG_HUGETLB_PAGE is not set
Signed-off-by: Fabio M. Di Nitto <fabbione@ubuntu.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:35 -08:00
David S. Miller
8b23427441 [SPARC64]: More TLB/TSB handling fixes.
The SUN4V convention with non-shared TSBs is that the context
bit of the TAG is clear.  So we have to choose an "invalid"
bit and initialize new TSBs appropriately.  Otherwise a zero
TAG looks "valid".

Make sure, for the window fixup cases, that we use the right
global registers and that we don't potentially trample on
the live global registers in etrap/rtrap handling (%g2 and
%g6) and that we put the missing virtual address properly
in %g5.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:34 -08:00
David S. Miller
7adb37fe80 [SPARC64]: Don't do anything in flush_ptrace_access() on SUN4V.
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:33 -08:00
David S. Miller
6c8927c963 [SPARC64]: Fix some SUN4V TLB handling bugs.
1) Add error return checking for TLB load hypervisor
   calls.

2) Don't fallthru to dtlb tsb miss handler from itlb tsb
   miss handler, oops.

3) On window fixups, propagate fault information to fixup
   handler correctly.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:13:32 -08:00