With commit c814a4c7c4, the meaning of tempX_max
was changed. It no longer returns the value of bits 8:15 of
MSR_IA32_TEMPERATURE_TARGET, but instead returns the value of CPU threshold
register T1. tempX_max_hyst was added to reflect the value of temperature
threshold register T0.
As it turns out, T0 and T1 are used on some systems, presumably by the BIOS.
Also, T0 and T1 don't have a well defined meaning. The thresholds may be used
as upper or lower limits, and it is not guaranteed that T0 <= T1. Thus, the new
attribute mapping does not reflect the actual usage of the threshold registers.
Also, register contents are changed during runtime by an entity other than the
hwmon driver, meaning the values cached by the driver do not reflect actual
register contents.
Revert most of c814a4c7c4 to address the problem.
Support for T0 and T1 will be added back in with a separate commit, using new
attribute names.
Signed-off-by: Guenter Roeck <guenter.roeck@ericsson.com>
Cc: Fenghua Yu <fenghua.yu@intel.com>
Cc: Durgadoss R <durgadoss.r@intel.com>
Acked-by: Jean Delvare <khali@linux-fr.org>
This patch adds the core and pkg support to coretemp.
These thresholds can be configured via the sysfs interfaces tempX_max
and tempX_max_hyst. An interrupt is generated when CPU temperature reaches
or crosses above tempX_max OR drops below tempX_max_hyst.
This patch is based on the documentation in IA Manual vol 3A, that can be
downloaded from here:
http://download.intel.com/design/processor/manuals/253668.pdf
Signed-off-by: Durgadoss R <durgadoss.r@intel.com>
Signed-off-by: Guenter Roeck <guenter.roeck@ericsson.com>
This patch merges the pkgtemp with coretemp driver.
The sysfs interfaces for all cores in the same pkg
are shown under one directory, in hwmon. It also
supports CONFIG_HOTPLUG_CPU. So, the sysfs interfaces
are created when each core comes online and are
removed when it goes offline.
Signed-off-by: Durgadoss R <durgadoss.r@intel.com>
Cc: Fenghua Yu <fenghua.yu@intel.com>
[guenter.roeck@ericsson.com: Fixed section reference errors]
Signed-off-by: Guenter Roeck <guenter.roeck@ericsson.com>
Following patch adds support for mobile Penryn CPUs. Intel documents this
poorly. I asked the Coretemp author for some help. This is totally untested and
may not work. Please test!
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Cc: Huaxu Wan <huaxu.wan@linux.intel.com>
Cc: Kent Liu <kent.liu@linux.intel.com>
Signed-off-by: Jean Delvare <khali@linux-fr.org>
This patch adds support for family 0x17, which has Penryn Core. It should also
cover the 8 cores Xeons.
Can someone test please? I think it should work.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Jean Delvare <khali@linux-fr.org>
Signed-off-by: Mark M. Hoffman <mhoffman@lightlink.com>
Following patch will add reporting of maximum temperature, at which all fans
should spin full speed. It may be non-physical temperature on Desktop/Server CPUs.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Jean Delvare <khali@linux-fr.org>
Signed-off-by: Mark M. Hoffman <mhoffman@lightlink.com>
This patch adds support for the Celeron 4xx based on Core 2 core.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Signed-off-by: Mark M. Hoffman <mhoffman@lightlink.com>
