Fix DPLL jitter correction programming. Previously,
omap3_noncore_dpll_program() stored the FREQSEL jitter correction
parameter to the wrong register. This caused jitter correction to be set
incorrectly and also caused the DPLL divider to be programmed incorrectly.
Also, fix DPLL divider programming. An off-by-one error existed in
omap3_noncore_dpll_program(), causing DPLLs to be programmed with a higher
divider than intended.
linux-omap source commit is 5c0ec88a2145cdf2f2c9cc5fae49635c4c2476c7.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Using sdti doesn't keep emu_pwrdm on if hardware supervised pwrdm
transitions are used. This causes sdti stop to work when power
management is initialized and hardware supervised pwrdm control is
enabled. This patch disables hardware supervised pwrdm control for
emu_pwrdm. Now emu_pwrdm is switched off on boot by software when it
is not used.
Signed-off-by: Jouni Hogander <jouni.hogander@nokia.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Fix the clockdomain autodep code to respect omap_chip platform flags.
Resolves "Unable to handle kernel paging request at virtual address
5f75706d" panic during power management initialization on OMAP2.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Enabling clock in a disabled power domain causes the power domain to be
turned on. However, the power transition is not always finished when
clk_enable() returns and this randomly crashes the kernel when an
interrupt happens right after the clk_enable, and the kernel tries to
read the irq status register for that domain.
Why the irq status register is inaccessible, I don't know. Also it
doesn't seem to be related to the module being not powered up, but to
the transition itself.
The same could perhaps happen after clk_disable also, but I have not
witnessed that.
The problem affects at least dss, cam and sgx clocks.
This change waits for the transition to be finished before returning
from omap2_clkdm_clk_enable().
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The SGX device on OMAP3 does not support retention, so remove RET from the
list of possible SGX power states. Problem debugged by Richard Woodruff
<r-woodruff2@ti.com>.
Signed-off-by: Richard Woodruff <r-woodruff2@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Each DPLL exists in its own powerdomain (cf 34xx TRM figure 4-18) and
clockdomain; so, create powerdomain and clockdomain structures for them.
Mark each DPLL clock as belonging to their respective DPLL clockdomain.
cf. 34xx TRM Table 4-27 (among other references).
linux-omap source commits are acdb615850b9b4f7d1ab68133a16be8c8c0e7419 and
a8798a48f33e9268dcc7f30a4b4a3ce4220fe0c9.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
sys_clkout2 belongs in the core_clkdm (3430 TRM section 4.7.2.2).
It's not clear whether it actually is in the CORE clockdomain, or whether
it is technically in a different clockdomain; but this is closer to
reality than the present configuration.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Add clockdomains for the CM and PRM. These will ultimately replace the
"wkup_clkdm", which appears to not actually exist on the hardware.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
struct clockdomain contains a struct powerdomain *pwrdm and const char
*pwrdm_name. The pwrdm_name is only used at initialization to look up
the appropriate pwrdm pointer. Combining these into a union saves
about 100 bytes on 3430SDP. This patch should not cause any change in
kernel function.
Updated to gracefully handle autodeps that contain invalid powerdomains,
per Russell King's review comments.
Boot-tested on BeagleBoard ES2.1.
linux-omap source commit is 718fc6cd4db902aa2242a736cc3feb8744a4c71a.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This patch adds a CPUfreq frequency-table implementation for OMAP2 by
walking the PRCM rate-table for available entries and adding them to a
CPUfreq table.
CPUfreq can then be used to manage switching between all the available
entries in the PRCM rate table. Either use the CPUfreq sysfs
interface directly, (see Section 3 of Documentation/cpu-freq/user-guide.txt)
or use the cpufrequtils package:
http://www.kernel.org/pub/linux/utils/kernel/cpufreq/cpufrequtils.html
Signed-off-by: Kevin Hilman <khilman@mvista.com>
Updated to try to use cpufreq_table if it exists.
linux-omap source commit is 77ce544fa48deb7a2003f454624e3ca10d37ab87.
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Filling the set_rate and round_rate fields of dpll4_m4_ck makes
this clock programmable through clk_set_rate(). This is needed
to give omapfb control over the dss1_alwon_fck rate.
This patch includes a fix from Tomi Valkeinen <tomi.valkeinen@nokia.com>.
linux-omap source commits are e42218d45afbc3e654e289e021e6b80c657b16c2 and
9d211b761b3cdf7736602ecf7e68f8a298c13278.
Signed-off-by: Måns Rullgård <mans@mansr.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@nokia.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Add CSI2 clock struct for handling it with clock API when TI PM is disabled.
linux-omap source commit is 8b20f4498928459276bd3366e3381ad595d23432.
Signed-off-by: Sergio Aguirre <saaguirre@ti.com>
Acked-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The GFX/SGX functional and interface clocks have different masks, for
some unknown reason, so split EN_SGX_SHIFT into one each for fclk and
iclk.
Correct according to the TRM and the far more important 'does this
actually work at all?' metric.
linux-omap source commit is de1121fdb899f762b9e717f44eaf3fae7c00cd3e.
Signed-off-by: Daniel Stone <daniel.stone@nokia.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Fix some bugs in the OMAP3 clock tree pertaining to the 96MHz clocks.
The 96MHz portion of the clock tree should now have reasonable
fidelity to the 34xx TRM Rev I.
One remaining question mark: it's not clear exactly which 96MHz source
clock the USIM uses. This patch sticks with the previous setting, which
seems reasonable.
linux-omap source commit is 15c706e8179ce238c3ba70a25846a36b73bd2359.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Remove usbhost_sar_fclk from the OMAP3 clock framework. The bit that
the clock was tweaking doesn't actually enable or disable a clock; it
controls whether the hardware will save and restore USBHOST state
when the powerdomain changes state. (That happens to coincidentally
enable a clock for the duration of the operation, hence the earlier
confusion.)
In place of the clock, mark the USBHOST powerdomain as supporting
hardware save-and-restore functionality.
linux-omap source commit is f3ceac86a9d425d101d606d87a5af44afef27179.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This patch adds a missing OMAP24xx clock, the SSI L4 interface clock,
as "ssi_l4_ick".
linux-omap source commit is ace129d39b3107d330d4cf6934385d13521f2fec.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Fix sparse & checkpatch warnings in OMAP2/3 PRCM & PM code. This mostly
consists of:
- converting pointer comparisons to integers in form similar to
(ptr == 0) to the standard idiom (!ptr)
- labeling a few non-static private functions as static
- adding prototypes for *_init() functions in the appropriate header
files, and getting rid of the corresponding open-coded extern
prototypes in other C files
- renaming the variable 'sclk' in mach-omap2/clock.c:omap2_get_apll_clkin
to avoid shadowing an earlier declaration
Clean up checkpatch issues. This mostly involves:
- converting some asm/ includes to linux/ includes
- cleaning up some whitespace
- getting rid of braces for conditionals with single following statements
Also take care of a few odds and ends, including:
- getting rid of unlikely() and likely() - none of this code is particularly
fast-path code, so the performance impact seems slim; and some of those
likely() and unlikely() indicators are probably not as accurate as the
ARM's branch predictor
- removing some superfluous casts
linux-omap source commit is 347df59f5d20fdf905afbc26b1328b0e28a8a01b.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Add non-CORE DPLL rate set code and M,N programming for OMAP3.
Connect it to OMAP34xx DPLLs 1, 2, 4, 5 via the clock framework.
You may see some warnings on rate sets from the freqsel code. The
table that TI presented in the 3430 TRM Rev F does not cover Fint <
750000, which definitely occurs in practice. However, the lack of this
freqsel case does not appear to impair the DPLL rate change.
linux-omap source commit is 689fe67c6d1ad8f52f7f7b139a3274b79bf3e784.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Rather than introducing a special 'mcbsp_clk' with code behind it in
mach-omap*/mcbsp.c to handle the SoC specifics, arrange for the mcbsp
driver to be like any other driver. mcbsp requests its fck and ick
clocks directly, and the SoC specific code deals with selecting the
correct clock.
There is one oddity to deal with - OMAP1 fiddles with the DSP clocks
and DSP reset, so we move this to the two callback functions.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Convert OMAP MMC driver to match clocks using the device ID and a
connection ID rather than a clock name. This allows us to eliminate
the OMAP1/OMAP2 differences for the function clock.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
propagate_rate() is recursive, so it makes sense to minimise the
amount of stack which is used for each recursion. So, rather than
recursing back into it from the ->recalc functions if RATE_PROPAGATES
is set, do that test at the higher level.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Move the clock propagation calls for set_parent and set_rate into
the core omap clock code, rather than having these calls scattered
throughout the OMAP1 and OMAP2 implementations.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The original code in omap2_clk_wait_ready() used to check the low 8
bits to determine whether they were within the FCLKEN or ICLKEN
registers. Specifically, the test is satisfied when these offsets
are used:
CM_FCLKEN, CM_FCLKEN1, CM_CLKEN, OMAP24XX_CM_FCLKEN2, CM_ICLKEN,
CM_ICLKEN1, CM_ICLKEN2, CM_ICLKEN3, OMAP24XX_CM_ICLKEN4
OMAP3430_CM_CLKEN_PLL, OMAP3430ES2_CM_CLKEN2
If one of these offsets isn't used, omap2_clk_wait_ready() merely
returns without doing anything. So we should use the non-wait clkops
version instead and eliminate that conditional.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Rather than employing run-time tests in omap2_clk_wait_ready() to
decide whether we need to wait for the clock to become ready, we
can set the .ops appropriately.
This change deals with the OMAP24xx and OMAP34xx conditionals only.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
PARENT_CONTROLS_CLOCK just makes enable/disable no-op, and is
functionally an alias for ALWAYS_ENABLED. This can be handled
in the same way, using clkops_null.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
... and use it for clocks which are ALWAYS_ENABLED. These clocks
use a non-NULL enable_reg pointer for other purposes (such as
selecting clock rates.)
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Collect up all the common enable/disable clock operation functions
into a separate operations structure.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
In omap24xx_cpu_suspend assembly routine, the r2 register which holds
the address of the SDRC_POWER reg is set to zero before the value is
written back triggering a fault due to writing to address zero.
It's hard to tell where this change was introduced since this file
has been moved and merged.
While this fix prevents a crash, suspend on my n810 is broken with
current kernels. I never come out of suspend.
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
By Ingo Molnar, interrupts are not masked by default.
(refer to 76d2160147)
But if interrupts are not masked, the processor can wake up while in
Suspend-to-RAM state by an external interrupt. For example, if an
OMAP3 board is connected to Host PC by USB and entered to Suspend-to-RAM
state, it wake up automatically by M_IRQ_92. The disable_irq() function
can't disable the interrupt in H/W level, So I modified
arch/arm/mach-omap2/irq.c
Signed-off-by: Kim Kyuwon <chammoru@gmail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
When 32 kHz timer is used the min_delta_ns should be initialized so
that it reflects the timer programming cost. A write to the timer
device will be usually posted, but it takes roughly 3 cycles before
it is effective. If the timer is reprogrammed before that, the CPU
will stall until the previous write completes. This was pointed out by
Richard Woodruff.
Since the lower bound for min_delta_ns is 1000, the change is visible
only with tick rates less than 3 MHz.
Also note that the old value is incorrect for 32 kHz also due to
a rounding error, and it can cause the timer queue to hang (due to
clockevent code trying to program the timer with zero ticks).
Signed-off-by: Aaro Koskinen <Aaro.Koskinen@nokia.com>
Reviewed-by: Richard Woodruff <r-woodruff2@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The naming accidentally broke while changing the name for the
driver to not to conflict with the other mmc driver.
Signed-off-by: Tony Lindgren <tony@atomide.com>
A spin_lock deadlock will occur when omap_mcbsp_request() is invoked.
omap_mcbsp_request()
\- clk_enable(mcbsp->clk) [takes and holds clockfw_lock]
\- omap2_clk_enable()
\- _omap2_clk_enable()
\- omap_mcbsp_clk_enable()
\- clk_enable(child clock) [tries for clockfw_lock again]
mcbsp_clk is a virtual clock and it comprises several child clocks. when
enable mcbsp_clk in omap_mcbsp_request(), the enable function of mcbsp_clk
will enable its child clocks, then the deadlock occurs.
The solution is to remove the virtual clock and enable these child clocks in
omap_mcbsp_request() directly.
Signed-off-by: Stanley.Miao <stanley.miao@windriver.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Fix compile by removing remaining omap specific gpio
calls. Based on earlier patches by Jarkko Nikula.
Also remove old GPIO key code, there is already a patch
to do this with gpio_keys.
Signed-off-by: Jarkko Nikula <jarkko.nikula@nokia.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
arch/arm/mach-at91/at91cap9.c:337: error: 'NR_AIC_IRQS' undeclared here (not in a function)
arch/arm/mach-at91/at91rm9200.c:301: error: 'NR_AIC_IRQS' undeclared here (not in a function)
arch/arm/mach-at91/at91sam9260.c:351: error: 'NR_AIC_IRQS' undeclared here (not in a function)
arch/arm/mach-at91/at91sam9261.c:287: error: 'NR_AIC_IRQS' undeclared here (not in a function)
arch/arm/mach-at91/at91sam9263.c:312: error: 'NR_AIC_IRQS' undeclared here (not in a function)
arch/arm/mach-at91/at91sam9rl.c:304: error: 'NR_AIC_IRQS' undeclared here (not in a function)
arch/arm/mach-h720x/h7202-eval.c:38: error: implicit declaration of function 'IRQ_CHAINED_GPIOB'
arch/arm/mach-ks8695/devices.c:46: error: 'KS8695_IRQ_WAN_RX_STATUS' undeclared here (not in a function)
arch/arm/mach-msm/devices.c:28: error: 'INT_UART1' undeclared here (not in a function)
arch/arm/mach-mx2/devices.c:233: error: 'MXC_GPIO_IRQ_START' undeclared here (not in a function)
arch/arm/mach-mx3/devices.c:128: error: 'MXC_GPIO_IRQ_START' undeclared here (not in a function)
arch/arm/mach-omap1/mcbsp.c:140: error: 'INT_730_McBSP1RX' undeclared here (not in a function)
arch/arm/mach-omap1/mcbsp.c:165: error: 'INT_McBSP1RX' undeclared here (not in a function)
arch/arm/mach-omap1/mcbsp.c:200: error: 'INT_McBSP1RX' undeclared here (not in a function)
arch/arm/mach-omap2/board-apollon.c:286: error: implicit declaration of function 'omap_set_gpio_direction'
arch/arm/mach-omap2/mcbsp.c:154: error: 'INT_24XX_MCBSP1_IRQ_RX' undeclared here (not in a function)
arch/arm/mach-omap2/mcbsp.c:181: error: 'INT_24XX_MCBSP1_IRQ_RX' undeclared here (not in a function)
arch/arm/mach-pxa/e350.c:36: error: 'IRQ_BOARD_START' undeclared here (not in a function)
arch/arm/plat-s3c/dev-i2c0.c:32: error: 'IRQ_IIC' undeclared here (not in a function)
...
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* 'i2c-next' of git://aeryn.fluff.org.uk/bjdooks/linux:
i2c-omap: fix type of irq handler function
i2c-s3c2410: Change IRQ to be plain integer.
i2c-s3c2410: Allow more than one i2c-s3c2410 adapter
i2c-s3c2410: Remove default platform data.
i2c-s3c2410: Use platform data for gpio configuration
i2c-s3c2410: Fixup style problems from checkpatch.pl
i2c-omap: Enable I2C wakeups for 34xx
i2c-omap: reprogram OCP_SYSCONFIG register after reset
i2c-omap: convert 'rev1' flag to generic 'rev' u8
i2c-omap: fix I2C timeouts due to recursive omap_i2c_{un,}idle()
i2c-omap: Clean-up i2c-omap
i2c-omap: Don't compile in OMAP15xx I2C ISR for non-OMAP15xx builds
i2c-omap: Mark init-only functions as __init
i2c-omap: Add support for omap34xx
i2c-omap: FIFO handling support and broken hw workaround for i2c-omap
i2c-omap: Add high-speed support to omap-i2c
i2c-omap: Close suspected race between omap_i2c_idle() and omap_i2c_isr()
i2c-omap: Do not use interruptible wait call in omap_i2c_xfer_msg
Fix up apparently-trivial conflict in drivers/i2c/busses/i2c-s3c2410.c
