36d68f64c4
Krait CPUs have a handful of L2 cache controller registers that live behind a cp15 based indirection register. First you program the indirection register (l2cpselr) to point the L2 'window' register (l2cpdr) at what you want to read/write. Then you read/write the 'window' register to do what you want. The l2cpselr register is not banked per-cpu so we must lock around accesses to it to prevent other CPUs from re-pointing l2cpdr underneath us. Cc: Mark Rutland <mark.rutland@arm.com> Cc: Russell King <linux@arm.linux.org.uk> Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Sricharan R <sricharan@codeaurora.org> Tested-by: Craig Tatlor <ctatlor97@gmail.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
22 lines
716 B
Makefile
22 lines
716 B
Makefile
# SPDX-License-Identifier: GPL-2.0
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#
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# Makefile for the linux kernel.
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#
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obj-y += firmware.o
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obj-$(CONFIG_SA1111) += sa1111.o
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obj-$(CONFIG_DMABOUNCE) += dmabounce.o
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obj-$(CONFIG_KRAIT_L2_ACCESSORS) += krait-l2-accessors.o
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obj-$(CONFIG_SHARP_LOCOMO) += locomo.o
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obj-$(CONFIG_SHARP_PARAM) += sharpsl_param.o
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obj-$(CONFIG_SHARP_SCOOP) += scoop.o
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obj-$(CONFIG_CPU_V7) += secure_cntvoff.o
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obj-$(CONFIG_PCI_HOST_ITE8152) += it8152.o
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obj-$(CONFIG_MCPM) += mcpm_head.o mcpm_entry.o mcpm_platsmp.o vlock.o
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CFLAGS_REMOVE_mcpm_entry.o = -pg
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AFLAGS_mcpm_head.o := -march=armv7-a
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AFLAGS_vlock.o := -march=armv7-a
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obj-$(CONFIG_BL_SWITCHER) += bL_switcher.o
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obj-$(CONFIG_BL_SWITCHER_DUMMY_IF) += bL_switcher_dummy_if.o
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