d4b34c6c84
S5P Samsung SoCs has a EPLL to support various PLL clock sources for other H/W blocks. Until now, to control EPLL, each of SoCs make their own functions in 'mach-s5pxxx/clock.c'. But some of functions, 'xxx_epll_get_rate()' and 'xxx_epll_enable()', are exactly same in all S5P SoCs, so this patch move these duplicated codes to common EPLL functions that use platform wide. Signed-off-by: Seungwhan Youn <sw.youn@samsung.com> Acked-by: Jassi Brar <jassi.brar@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
66 lines
1.9 KiB
C
66 lines
1.9 KiB
C
/* linux/arch/arm/mach-s5p64x0/include/mach/regs-clock.h
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*
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* Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* S5P64X0 - Clock register definitions
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_ARCH_REGS_CLOCK_H
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#define __ASM_ARCH_REGS_CLOCK_H __FILE__
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#include <mach/map.h>
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#define S5P_CLKREG(x) (S3C_VA_SYS + (x))
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#define S5P64X0_APLL_CON S5P_CLKREG(0x0C)
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#define S5P64X0_MPLL_CON S5P_CLKREG(0x10)
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#define S5P64X0_EPLL_CON S5P_CLKREG(0x14)
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#define S5P64X0_EPLL_CON_K S5P_CLKREG(0x18)
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#define S5P64X0_CLK_SRC0 S5P_CLKREG(0x1C)
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#define S5P64X0_CLK_DIV0 S5P_CLKREG(0x20)
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#define S5P64X0_CLK_DIV1 S5P_CLKREG(0x24)
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#define S5P64X0_CLK_DIV2 S5P_CLKREG(0x28)
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#define S5P64X0_CLK_GATE_HCLK0 S5P_CLKREG(0x30)
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#define S5P64X0_CLK_GATE_PCLK S5P_CLKREG(0x34)
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#define S5P64X0_CLK_GATE_SCLK0 S5P_CLKREG(0x38)
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#define S5P64X0_CLK_GATE_MEM0 S5P_CLKREG(0x3C)
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#define S5P64X0_CLK_DIV3 S5P_CLKREG(0x40)
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#define S5P64X0_CLK_GATE_HCLK1 S5P_CLKREG(0x44)
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#define S5P64X0_CLK_GATE_SCLK1 S5P_CLKREG(0x48)
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#define S5P6450_DPLL_CON S5P_CLKREG(0x50)
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#define S5P6450_DPLL_CON_K S5P_CLKREG(0x54)
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#define S5P64X0_CLK_SRC1 S5P_CLKREG(0x10C)
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#define S5P64X0_SYS_ID S5P_CLKREG(0x118)
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#define S5P64X0_SYS_OTHERS S5P_CLKREG(0x11C)
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#define S5P64X0_PWR_CFG S5P_CLKREG(0x804)
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#define S5P64X0_OTHERS S5P_CLKREG(0x900)
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#define S5P64X0_CLKDIV0_HCLK_SHIFT (8)
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#define S5P64X0_CLKDIV0_HCLK_MASK (0xF << S5P64X0_CLKDIV0_HCLK_SHIFT)
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#define S5P64X0_OTHERS_USB_SIG_MASK (1 << 16)
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/* Compatibility defines */
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#define ARM_CLK_DIV S5P64X0_CLK_DIV0
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#define ARM_DIV_RATIO_SHIFT 0
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#define ARM_DIV_MASK (0xF << ARM_DIV_RATIO_SHIFT)
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#define S5P_EPLL_CON S5P64X0_EPLL_CON
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#endif /* __ASM_ARCH_REGS_CLOCK_H */
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