181193f398
The ARM perf-events framework provides support for a number of different PMUs using struct arm_pmu. The char *name field of this struct can be used to identify the PMU, but this is cumbersome if used outside of perf. This patch replaces the name string for a PMU with an enum, which holds a unique ID for the PMU being represented. This ID can be used to index an array of names within perf, so no functionality is lost. The presence of the ID field, allows other kernel subsystems [currently oprofile] to use their own mappings for the PMU name. Cc: Jean Pihet <jpihet@mvista.com> Acked-by: Jamie Iles <jamie.iles@picochip.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
46 lines
1.2 KiB
C
46 lines
1.2 KiB
C
/*
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* linux/arch/arm/include/asm/perf_event.h
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*
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* Copyright (C) 2009 picoChip Designs Ltd, Jamie Iles
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#ifndef __ARM_PERF_EVENT_H__
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#define __ARM_PERF_EVENT_H__
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/*
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* NOP: on *most* (read: all supported) ARM platforms, the performance
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* counter interrupts are regular interrupts and not an NMI. This
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* means that when we receive the interrupt we can call
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* perf_event_do_pending() that handles all of the work with
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* interrupts enabled.
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*/
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static inline void
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set_perf_event_pending(void)
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{
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}
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/* ARM performance counters start from 1 (in the cp15 accesses) so use the
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* same indexes here for consistency. */
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#define PERF_EVENT_INDEX_OFFSET 1
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/* ARM perf PMU IDs for use by internal perf clients. */
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enum arm_perf_pmu_ids {
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ARM_PERF_PMU_ID_XSCALE1 = 0,
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ARM_PERF_PMU_ID_XSCALE2,
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ARM_PERF_PMU_ID_V6,
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ARM_PERF_PMU_ID_V6MP,
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ARM_PERF_PMU_ID_CA8,
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ARM_PERF_PMU_ID_CA9,
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ARM_NUM_PMU_IDS,
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};
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extern enum arm_perf_pmu_ids
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armpmu_get_pmu_id(void);
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#endif /* __ARM_PERF_EVENT_H__ */
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