198a0a927a
We can test bits 27:25 and 20 of the instruction at the same time; there's no need to separate out the check of bit 20. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
41 lines
1.1 KiB
ArmAsm
41 lines
1.1 KiB
ArmAsm
/*
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* The ARM LDRD and Thumb LDRSB instructions use bit 20/11 (ARM/Thumb)
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* differently than every other instruction, so it is set to 0 (write)
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* even though the instructions are read instructions. This means that
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* during an abort the instructions will be treated as a write and the
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* handler will raise a signal from unwriteable locations if they
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* fault. We have to specifically check for these instructions
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* from the abort handlers to treat them properly.
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*
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*/
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.macro do_thumb_abort, fsr, pc, psr, tmp
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tst \psr, #PSR_T_BIT
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beq not_thumb
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ldrh \tmp, [\pc] @ Read aborted Thumb instruction
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and \tmp, \tmp, # 0xfe00 @ Mask opcode field
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cmp \tmp, # 0x5600 @ Is it ldrsb?
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orreq \tmp, \tmp, #1 << 11 @ Set L-bit if yes
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tst \tmp, #1 << 11 @ L = 0 -> write
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orreq \psr, \psr, #1 << 11 @ yes.
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mov pc, lr
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not_thumb:
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.endm
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/*
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* We check for the following instruction encoding for LDRD.
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*
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* [27:25] == 000
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* [7:4] == 1101
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* [20] == 0
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*/
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.macro do_ldrd_abort, tmp, insn
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tst \insn, #0x0e100000 @ [27:25,20] == 0
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bne not_ldrd
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and \tmp, \insn, #0x000000f0 @ [7:4] == 1101
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cmp \tmp, #0x000000d0
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moveq pc, lr
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not_ldrd:
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.endm
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