482b05dd53
Replaced check_user_space() + __check_access_register with the new check_space(). The old functions made wrong assumptions about kernel and user space when the kernel and user address spaces are switched (kernel in home space, user in primary/secondary space). Secondly the user process can switch to the accress register mode if it is running in primary or secondary mode. In addition it can load an arbitrary value to the access registers. If any other value than 0 for primary space or 1 for secondary space is loaded and memory is accessed using the base register related to the access register, the program should be terminated with a SIGSEGV. To achieve that the DUALD pointer in the DUCT and the PSALD pointer in the PASTE need to point to an array of 8 invalid access-list entries to get a ALEN-translation exception if an invalid alet is used. Signed-off-by: Gerald Schaefer <geraldsc@de.ibm.com> Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
192 lines
4.9 KiB
ArmAsm
192 lines
4.9 KiB
ArmAsm
/*
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* arch/s390/kernel/head64.S
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*
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* Copyright (C) IBM Corp. 1999,2006
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*
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* Author(s): Hartmut Penner <hp@de.ibm.com>
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* Martin Schwidefsky <schwidefsky@de.ibm.com>
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* Rob van der Heij <rvdhei@iae.nl>
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* Heiko Carstens <heiko.carstens@de.ibm.com>
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*
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*/
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#
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# startup-code at 0x10000, running in absolute addressing mode
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# this is called either by the ipl loader or directly by PSW restart
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# or linload or SALIPL
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#
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.org 0x10000
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startup:basr %r13,0 # get base
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.LPG0: l %r13,0f-.LPG0(%r13)
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b 0(%r13)
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0: .long startup_continue
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#
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# params at 10400 (setup.h)
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#
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.org PARMAREA
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.quad 0 # IPL_DEVICE
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.quad 0 # INITRD_START
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.quad 0 # INITRD_SIZE
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.org COMMAND_LINE
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.byte "root=/dev/ram0 ro"
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.byte 0
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.org 0x11000
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startup_continue:
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basr %r13,0 # get base
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.LPG1: sll %r13,1 # remove high order bit
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srl %r13,1
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lhi %r1,1 # mode 1 = esame
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mvi __LC_AR_MODE_ID,1 # set esame flag
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slr %r0,%r0 # set cpuid to zero
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sigp %r1,%r0,0x12 # switch to esame mode
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sam64 # switch to 64 bit mode
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lctlg %c0,%c15,.Lctl-.LPG1(%r13) # load control registers
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lg %r12,.Lparmaddr-.LPG1(%r13) # pointer to parameter area
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# move IPL device to lowcore
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mvc __LC_IPLDEV(4),IPL_DEVICE+4-PARMAREA(%r12)
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#
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# Setup stack
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#
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larl %r15,init_thread_union
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lg %r14,__TI_task(%r15) # cache current in lowcore
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stg %r14,__LC_CURRENT
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aghi %r15,1<<(PAGE_SHIFT+THREAD_ORDER) # init_task_union + THREAD_SIZE
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stg %r15,__LC_KERNEL_STACK # set end of kernel stack
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aghi %r15,-160
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xc __SF_BACKCHAIN(4,%r15),__SF_BACKCHAIN(%r15) # clear backchain
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#
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# Save ipl parameters, clear bss memory, initialize storage key for kernel pages,
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# and create a kernel NSS if the SAVESYS= parm is defined
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#
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brasl %r14,startup_init
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# set program check new psw mask
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mvc __LC_PGM_NEW_PSW(8),.Lpcmsk-.LPG1(%r13)
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larl %r12,machine_flags
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#
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# find out if we have the MVPG instruction
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#
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la %r1,0f-.LPG1(%r13) # set program check address
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stg %r1,__LC_PGM_NEW_PSW+8
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sgr %r0,%r0
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lghi %r1,0
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lghi %r2,0
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mvpg %r1,%r2 # test MVPG instruction
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oi 7(%r12),16 # set MVPG flag
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0:
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#
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# find out if the diag 0x44 works in 64 bit mode
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#
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la %r1,0f-.LPG1(%r13) # set program check address
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stg %r1,__LC_PGM_NEW_PSW+8
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diag 0,0,0x44 # test diag 0x44
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oi 7(%r12),32 # set diag44 flag
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0:
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#
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# find out if we have the IDTE instruction
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#
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la %r1,0f-.LPG1(%r13) # set program check address
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stg %r1,__LC_PGM_NEW_PSW+8
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.long 0xb2b10000 # store facility list
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tm 0xc8,0x08 # check bit for clearing-by-ASCE
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bno 0f-.LPG1(%r13)
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lhi %r1,2094
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lhi %r2,0
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.long 0xb98e2001
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oi 7(%r12),0x80 # set IDTE flag
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0:
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#
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# find out if the diag 0x9c is available
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#
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la %r1,0f-.LPG1(%r13) # set program check address
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stg %r1,__LC_PGM_NEW_PSW+8
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stap __LC_CPUID+4 # store cpu address
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lh %r1,__LC_CPUID+4
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diag %r1,0,0x9c # test diag 0x9c
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oi 6(%r12),1 # set diag9c flag
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0:
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#
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# find out if we have the MVCOS instruction
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#
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la %r1,0f-.LPG1(%r13) # set program check address
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stg %r1,__LC_PGM_NEW_PSW+8
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.short 0xc800 # mvcos 0(%r0),0(%r0),%r0
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.short 0x0000
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.short 0x0000
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0: tm 0x8f,0x13 # special-operation exception?
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bno 1f-.LPG1(%r13) # if yes, MVCOS is present
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oi 6(%r12),2 # set MVCOS flag
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1:
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lpswe .Lentry-.LPG1(13) # jump to _stext in primary-space,
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# virtual and never return ...
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.align 16
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.Lentry:.quad 0x0000000180000000,_stext
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.Lctl: .quad 0x04b50002 # cr0: various things
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.quad 0 # cr1: primary space segment table
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.quad .Lduct # cr2: dispatchable unit control table
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.quad 0 # cr3: instruction authorization
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.quad 0 # cr4: instruction authorization
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.quad .Lduct # cr5: primary-aste origin
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.quad 0 # cr6: I/O interrupts
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.quad 0 # cr7: secondary space segment table
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.quad 0 # cr8: access registers translation
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.quad 0 # cr9: tracing off
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.quad 0 # cr10: tracing off
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.quad 0 # cr11: tracing off
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.quad 0 # cr12: tracing off
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.quad 0 # cr13: home space segment table
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.quad 0xc0000000 # cr14: machine check handling off
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.quad 0 # cr15: linkage stack operations
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.Lpcmsk:.quad 0x0000000180000000
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.L4malign:.quad 0xffffffffffc00000
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.Lscan2g:.quad 0x80000000 + 0x20000 - 8 # 2GB + 128K - 8
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.Lnop: .long 0x07000700
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.Lparmaddr:
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.quad PARMAREA
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.align 64
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.Lduct: .long 0,0,0,0,.Lduald,0,0,0
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.long 0,0,0,0,0,0,0,0
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.align 128
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.Lduald:.rept 8
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.long 0x80000000,0,0,0 # invalid access-list entries
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.endr
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.org 0x12000
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.globl _ehead
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_ehead:
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#ifdef CONFIG_SHARED_KERNEL
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.org 0x100000
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#endif
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#
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# startup-code, running in absolute addressing mode
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#
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.globl _stext
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_stext: basr %r13,0 # get base
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.LPG3:
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# check control registers
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stctg %c0,%c15,0(%r15)
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oi 6(%r15),0x40 # enable sigp emergency signal
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oi 4(%r15),0x10 # switch on low address proctection
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lctlg %c0,%c15,0(%r15)
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lam 0,15,.Laregs-.LPG3(%r13) # load acrs needed by uaccess
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brasl %r14,start_kernel # go to C code
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#
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# We returned from start_kernel ?!? PANIK
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#
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basr %r13,0
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lpswe .Ldw-.(%r13) # load disabled wait psw
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.align 8
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.Ldw: .quad 0x0002000180000000,0x0000000000000000
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.Laregs:.long 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
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