6c2b374d74
Patch 3 implements the core part of PCI-Express AER and aerdrv port service driver. When a root port service device is probed, the aerdrv will call request_irq to register irq handler for AER error interrupt. When a device sends an PCI-Express error message to the root port, the root port will trigger an interrupt, by either MSI or IO-APIC, then kernel would run the irq handler. The handler collects root error status register and schedules a work. The work will call the core part to process the error based on its type (Correctable/non-fatal/fatal). As for Correctable errors, the patch chooses to just clear the correctable error status register of the device. As for the non-fatal error, the patch follows generic PCI error handler rules to call the error callback functions of the endpoint's driver. If the device is a bridge, the patch chooses to broadcast the error to downstream devices. As for the fatal error, the patch resets the pci-express link and follows generic PCI error handler rules to call the error callback functions of the endpoint's driver. If the device is a bridge, the patch chooses to broadcast the error to downstream devices. Signed-off-by: Zhang Yanmin <yanmin.zhang@intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
126 lines
3.1 KiB
C
126 lines
3.1 KiB
C
/*
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* Copyright (C) 2006 Intel Corp.
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* Tom Long Nguyen (tom.l.nguyen@intel.com)
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* Zhang Yanmin (yanmin.zhang@intel.com)
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*
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*/
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#ifndef _AERDRV_H_
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#define _AERDRV_H_
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#include <linux/pcieport_if.h>
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#include <linux/aer.h>
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#define AER_NONFATAL 0
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#define AER_FATAL 1
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#define AER_CORRECTABLE 2
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#define AER_UNCORRECTABLE 4
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#define AER_ERROR_MASK 0x001fffff
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#define AER_ERROR(d) (d & AER_ERROR_MASK)
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#define OSC_METHOD_RUN_SUCCESS 0
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#define OSC_METHOD_NOT_SUPPORTED 1
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#define OSC_METHOD_RUN_FAILURE 2
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/* Root Error Status Register Bits */
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#define ROOT_ERR_STATUS_MASKS 0x0f
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#define SYSTEM_ERROR_INTR_ON_MESG_MASK (PCI_EXP_RTCTL_SECEE| \
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PCI_EXP_RTCTL_SENFEE| \
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PCI_EXP_RTCTL_SEFEE)
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#define ROOT_PORT_INTR_ON_MESG_MASK (PCI_ERR_ROOT_CMD_COR_EN| \
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PCI_ERR_ROOT_CMD_NONFATAL_EN| \
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PCI_ERR_ROOT_CMD_FATAL_EN)
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#define ERR_COR_ID(d) (d & 0xffff)
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#define ERR_UNCOR_ID(d) (d >> 16)
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#define AER_SUCCESS 0
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#define AER_UNSUCCESS 1
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#define AER_ERROR_SOURCES_MAX 100
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#define AER_LOG_TLP_MASKS (PCI_ERR_UNC_POISON_TLP| \
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PCI_ERR_UNC_ECRC| \
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PCI_ERR_UNC_UNSUP| \
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PCI_ERR_UNC_COMP_ABORT| \
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PCI_ERR_UNC_UNX_COMP| \
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PCI_ERR_UNC_MALF_TLP)
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/* AER Error Info Flags */
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#define AER_TLP_HEADER_VALID_FLAG 0x00000001
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#define AER_MULTI_ERROR_VALID_FLAG 0x00000002
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#define ERR_CORRECTABLE_ERROR_MASK 0x000031c1
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#define ERR_UNCORRECTABLE_ERROR_MASK 0x001ff010
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struct header_log_regs {
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unsigned int dw0;
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unsigned int dw1;
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unsigned int dw2;
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unsigned int dw3;
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};
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struct aer_err_info {
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int severity; /* 0:NONFATAL | 1:FATAL | 2:COR */
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int flags;
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unsigned int status; /* COR/UNCOR Error Status */
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struct header_log_regs tlp; /* TLP Header */
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};
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struct aer_err_source {
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unsigned int status;
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unsigned int id;
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};
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struct aer_rpc {
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struct pcie_device *rpd; /* Root Port device */
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struct work_struct dpc_handler;
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struct aer_err_source e_sources[AER_ERROR_SOURCES_MAX];
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unsigned short prod_idx; /* Error Producer Index */
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unsigned short cons_idx; /* Error Consumer Index */
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int isr;
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spinlock_t e_lock; /*
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* Lock access to Error Status/ID Regs
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* and error producer/consumer index
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*/
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struct mutex rpc_mutex; /*
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* only one thread could do
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* recovery on the same
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* root port hierachy
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*/
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wait_queue_head_t wait_release;
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};
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struct aer_broadcast_data {
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enum pci_channel_state state;
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enum pci_ers_result result;
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};
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static inline pci_ers_result_t merge_result(enum pci_ers_result orig,
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enum pci_ers_result new)
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{
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switch (orig) {
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case PCI_ERS_RESULT_CAN_RECOVER:
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case PCI_ERS_RESULT_RECOVERED:
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orig = new;
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break;
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case PCI_ERS_RESULT_DISCONNECT:
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if (new == PCI_ERS_RESULT_NEED_RESET)
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orig = new;
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break;
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default:
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break;
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}
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return orig;
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}
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extern struct bus_type pcie_port_bus_type;
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extern void aer_enable_rootport(struct aer_rpc *rpc);
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extern void aer_delete_rootport(struct aer_rpc *rpc);
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extern int aer_init(struct pcie_device *dev);
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extern void aer_isr(void *context);
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extern void aer_print_error(struct pci_dev *dev, struct aer_err_info *info);
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extern int aer_osc_setup(struct pci_dev *dev);
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#endif //_AERDRV_H_
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