580ff0eea1
Now that the coherency_init() function is called a bit earlier, we can actually read the physical address of the coherency unit registers from the Device Tree, and communicate that to the headsmp.S code, which avoids hardcoding a physical address. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Will Deacon <will.deacon@arm.com> Acked-by: Nicolas Pitre <nico@linaro.org> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
50 lines
1.3 KiB
ArmAsm
50 lines
1.3 KiB
ArmAsm
/*
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* SMP support: Entry point for secondary CPUs
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*
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* Copyright (C) 2012 Marvell
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*
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* Yehuda Yitschak <yehuday@marvell.com>
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* Gregory CLEMENT <gregory.clement@free-electrons.com>
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* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*
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* This file implements the assembly entry point for secondary CPUs in
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* an SMP kernel. The only thing we need to do is to add the CPU to
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* the coherency fabric by writing to 2 registers. Currently the base
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* register addresses are hard coded due to the early initialisation
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* problems.
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*/
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#include <linux/linkage.h>
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#include <linux/init.h>
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__CPUINIT
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/*
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* Armada XP specific entry point for secondary CPUs.
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* We add the CPU to the coherency fabric and then jump to secondary
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* startup
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*/
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ENTRY(armada_xp_secondary_startup)
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/* Get coherency fabric base physical address */
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adr r0, 1f
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ldr r1, [r0]
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ldr r0, [r0, r1]
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/* Read CPU id */
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mrc p15, 0, r1, c0, c0, 5
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and r1, r1, #0xF
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/* Add CPU to coherency fabric */
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bl ll_set_cpu_coherent
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b secondary_startup
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ENDPROC(armada_xp_secondary_startup)
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.align 2
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1:
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.long coherency_phys_base - .
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