23e5bc03e3
Copy the SoC specific timer code from Bonito board code to r8a7740 setup code. This makes is possible to share the SoC specific timer code across boards. The Bonito specific timer setup code tied to the FPGA is kept as-is. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
398 lines
8.8 KiB
C
398 lines
8.8 KiB
C
/*
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* R8A7740 processor support
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*
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* Copyright (C) 2011 Renesas Solutions Corp.
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* Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <linux/delay.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/platform_device.h>
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#include <linux/serial_sci.h>
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#include <linux/sh_timer.h>
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#include <mach/r8a7740.h>
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#include <mach/common.h>
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#include <asm/mach-types.h>
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#include <asm/mach/map.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/time.h>
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static struct map_desc r8a7740_io_desc[] __initdata = {
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/*
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* for CPGA/INTC/PFC
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* 0xe6000000-0xefffffff -> 0xe6000000-0xefffffff
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*/
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{
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.virtual = 0xe6000000,
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.pfn = __phys_to_pfn(0xe6000000),
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.length = 160 << 20,
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.type = MT_DEVICE_NONSHARED
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},
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#ifdef CONFIG_CACHE_L2X0
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/*
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* for l2x0_init()
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* 0xf0100000-0xf0101000 -> 0xf0002000-0xf0003000
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*/
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{
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.virtual = 0xf0002000,
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.pfn = __phys_to_pfn(0xf0100000),
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.length = PAGE_SIZE,
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.type = MT_DEVICE_NONSHARED
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},
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#endif
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};
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void __init r8a7740_map_io(void)
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{
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iotable_init(r8a7740_io_desc, ARRAY_SIZE(r8a7740_io_desc));
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}
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/* SCIFA0 */
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static struct plat_sci_port scif0_platform_data = {
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.mapbase = 0xe6c40000,
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.flags = UPF_BOOT_AUTOCONF,
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.scscr = SCSCR_RE | SCSCR_TE,
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.scbrr_algo_id = SCBRR_ALGO_4,
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.type = PORT_SCIFA,
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.irqs = SCIx_IRQ_MUXED(evt2irq(0x0c00)),
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};
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static struct platform_device scif0_device = {
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.name = "sh-sci",
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.id = 0,
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.dev = {
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.platform_data = &scif0_platform_data,
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},
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};
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/* SCIFA1 */
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static struct plat_sci_port scif1_platform_data = {
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.mapbase = 0xe6c50000,
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.flags = UPF_BOOT_AUTOCONF,
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.scscr = SCSCR_RE | SCSCR_TE,
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.scbrr_algo_id = SCBRR_ALGO_4,
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.type = PORT_SCIFA,
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.irqs = SCIx_IRQ_MUXED(evt2irq(0x0c20)),
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};
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static struct platform_device scif1_device = {
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.name = "sh-sci",
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.id = 1,
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.dev = {
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.platform_data = &scif1_platform_data,
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},
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};
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/* SCIFA2 */
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static struct plat_sci_port scif2_platform_data = {
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.mapbase = 0xe6c60000,
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.flags = UPF_BOOT_AUTOCONF,
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.scscr = SCSCR_RE | SCSCR_TE,
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.scbrr_algo_id = SCBRR_ALGO_4,
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.type = PORT_SCIFA,
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.irqs = SCIx_IRQ_MUXED(evt2irq(0x0c40)),
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};
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static struct platform_device scif2_device = {
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.name = "sh-sci",
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.id = 2,
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.dev = {
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.platform_data = &scif2_platform_data,
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},
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};
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/* SCIFA3 */
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static struct plat_sci_port scif3_platform_data = {
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.mapbase = 0xe6c70000,
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.flags = UPF_BOOT_AUTOCONF,
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.scscr = SCSCR_RE | SCSCR_TE,
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.scbrr_algo_id = SCBRR_ALGO_4,
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.type = PORT_SCIFA,
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.irqs = SCIx_IRQ_MUXED(evt2irq(0x0c60)),
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};
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static struct platform_device scif3_device = {
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.name = "sh-sci",
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.id = 3,
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.dev = {
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.platform_data = &scif3_platform_data,
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},
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};
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/* SCIFA4 */
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static struct plat_sci_port scif4_platform_data = {
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.mapbase = 0xe6c80000,
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.flags = UPF_BOOT_AUTOCONF,
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.scscr = SCSCR_RE | SCSCR_TE,
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.scbrr_algo_id = SCBRR_ALGO_4,
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.type = PORT_SCIFA,
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.irqs = SCIx_IRQ_MUXED(evt2irq(0x0d20)),
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};
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static struct platform_device scif4_device = {
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.name = "sh-sci",
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.id = 4,
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.dev = {
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.platform_data = &scif4_platform_data,
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},
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};
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/* SCIFA5 */
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static struct plat_sci_port scif5_platform_data = {
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.mapbase = 0xe6cb0000,
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.flags = UPF_BOOT_AUTOCONF,
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.scscr = SCSCR_RE | SCSCR_TE,
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.scbrr_algo_id = SCBRR_ALGO_4,
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.type = PORT_SCIFA,
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.irqs = SCIx_IRQ_MUXED(evt2irq(0x0d40)),
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};
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static struct platform_device scif5_device = {
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.name = "sh-sci",
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.id = 5,
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.dev = {
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.platform_data = &scif5_platform_data,
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},
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};
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/* SCIFA6 */
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static struct plat_sci_port scif6_platform_data = {
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.mapbase = 0xe6cc0000,
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.flags = UPF_BOOT_AUTOCONF,
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.scscr = SCSCR_RE | SCSCR_TE,
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.scbrr_algo_id = SCBRR_ALGO_4,
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.type = PORT_SCIFA,
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.irqs = SCIx_IRQ_MUXED(evt2irq(0x04c0)),
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};
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static struct platform_device scif6_device = {
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.name = "sh-sci",
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.id = 6,
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.dev = {
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.platform_data = &scif6_platform_data,
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},
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};
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/* SCIFA7 */
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static struct plat_sci_port scif7_platform_data = {
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.mapbase = 0xe6cd0000,
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.flags = UPF_BOOT_AUTOCONF,
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.scscr = SCSCR_RE | SCSCR_TE,
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.scbrr_algo_id = SCBRR_ALGO_4,
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.type = PORT_SCIFA,
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.irqs = SCIx_IRQ_MUXED(evt2irq(0x04e0)),
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};
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static struct platform_device scif7_device = {
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.name = "sh-sci",
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.id = 7,
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.dev = {
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.platform_data = &scif7_platform_data,
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},
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};
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/* SCIFB */
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static struct plat_sci_port scifb_platform_data = {
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.mapbase = 0xe6c30000,
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.flags = UPF_BOOT_AUTOCONF,
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.scscr = SCSCR_RE | SCSCR_TE,
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.scbrr_algo_id = SCBRR_ALGO_4,
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.type = PORT_SCIFB,
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.irqs = SCIx_IRQ_MUXED(evt2irq(0x0d60)),
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};
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static struct platform_device scifb_device = {
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.name = "sh-sci",
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.id = 8,
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.dev = {
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.platform_data = &scifb_platform_data,
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},
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};
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/* CMT */
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static struct sh_timer_config cmt10_platform_data = {
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.name = "CMT10",
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.channel_offset = 0x10,
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.timer_bit = 0,
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.clockevent_rating = 125,
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.clocksource_rating = 125,
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};
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static struct resource cmt10_resources[] = {
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[0] = {
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.name = "CMT10",
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.start = 0xe6138010,
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.end = 0xe613801b,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = evt2irq(0x0b00),
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device cmt10_device = {
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.name = "sh_cmt",
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.id = 10,
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.dev = {
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.platform_data = &cmt10_platform_data,
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},
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.resource = cmt10_resources,
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.num_resources = ARRAY_SIZE(cmt10_resources),
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};
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static struct platform_device *r8a7740_early_devices[] __initdata = {
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&scif0_device,
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&scif1_device,
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&scif2_device,
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&scif3_device,
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&scif4_device,
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&scif5_device,
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&scif6_device,
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&scif7_device,
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&scifb_device,
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&cmt10_device,
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};
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/* I2C */
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static struct resource i2c0_resources[] = {
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[0] = {
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.name = "IIC0",
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.start = 0xfff20000,
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.end = 0xfff20425 - 1,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = intcs_evt2irq(0xe00),
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.end = intcs_evt2irq(0xe60),
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct resource i2c1_resources[] = {
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[0] = {
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.name = "IIC1",
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.start = 0xe6c20000,
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.end = 0xe6c20425 - 1,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = evt2irq(0x780), /* IIC1_ALI1 */
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.end = evt2irq(0x7e0), /* IIC1_DTEI1 */
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device i2c0_device = {
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.name = "i2c-sh_mobile",
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.id = 0,
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.resource = i2c0_resources,
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.num_resources = ARRAY_SIZE(i2c0_resources),
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};
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static struct platform_device i2c1_device = {
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.name = "i2c-sh_mobile",
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.id = 1,
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.resource = i2c1_resources,
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.num_resources = ARRAY_SIZE(i2c1_resources),
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};
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static struct platform_device *r8a7740_late_devices[] __initdata = {
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&i2c0_device,
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&i2c1_device,
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};
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#define ICCR 0x0004
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#define ICSTART 0x0070
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#define i2c_read(reg, offset) ioread8(reg + offset)
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#define i2c_write(reg, offset, data) iowrite8(data, reg + offset)
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/*
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* r8a7740 chip has lasting errata on I2C I/O pad reset.
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* this is work-around for it.
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*/
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static void r8a7740_i2c_workaround(struct platform_device *pdev)
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{
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struct resource *res;
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void __iomem *reg;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (unlikely(!res)) {
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pr_err("r8a7740 i2c workaround fail (cannot find resource)\n");
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return;
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}
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reg = ioremap(res->start, resource_size(res));
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if (unlikely(!reg)) {
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pr_err("r8a7740 i2c workaround fail (cannot map IO)\n");
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return;
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}
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i2c_write(reg, ICCR, i2c_read(reg, ICCR) | 0x80);
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i2c_read(reg, ICCR); /* dummy read */
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i2c_write(reg, ICSTART, i2c_read(reg, ICSTART) | 0x10);
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i2c_read(reg, ICSTART); /* dummy read */
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mdelay(100);
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i2c_write(reg, ICCR, 0x01);
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i2c_read(reg, ICCR);
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i2c_write(reg, ICSTART, 0x00);
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i2c_read(reg, ICSTART);
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i2c_write(reg, ICCR, 0x10);
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mdelay(100);
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i2c_write(reg, ICCR, 0x00);
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mdelay(100);
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i2c_write(reg, ICCR, 0x10);
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mdelay(100);
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iounmap(reg);
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}
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void __init r8a7740_add_standard_devices(void)
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{
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/* I2C work-around */
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r8a7740_i2c_workaround(&i2c0_device);
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r8a7740_i2c_workaround(&i2c1_device);
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platform_add_devices(r8a7740_early_devices,
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ARRAY_SIZE(r8a7740_early_devices));
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platform_add_devices(r8a7740_late_devices,
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ARRAY_SIZE(r8a7740_late_devices));
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}
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static void __init r8a7740_earlytimer_init(void)
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{
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r8a7740_clock_init(0);
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shmobile_earlytimer_init();
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}
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void __init r8a7740_add_early_devices(void)
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{
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early_platform_add_devices(r8a7740_early_devices,
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ARRAY_SIZE(r8a7740_early_devices));
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/* setup early console here as well */
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shmobile_setup_console();
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/* override timer setup with soc-specific code */
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shmobile_timer.init = r8a7740_earlytimer_init;
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}
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