41ba653f24
The current cache options don't really represent the hardware features. They end up setting different aspects of the hardware so that the end result is to turn on/off the cache. Unfortunately, when we hit cache problems with the hardware, it's difficult to test different settings to root cause the problem. The current settings also don't cleanly allow for different caching behaviors with different regions of memory. So split the configure options such that they properly reflect the settings that are applied to the hardware. Signed-off-by: Jie Zhang <jie.zhang@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
121 lines
4.3 KiB
C
121 lines
4.3 KiB
C
/*
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* File: include/asm-blackfin/cacheflush.h
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* Based on: include/asm-m68knommu/cacheflush.h
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* Author: LG Soft India
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* Copyright (C) 2004 Analog Devices Inc.
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* Created: Tue Sep 21 2004
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* Description: Blackfin low-level cache routines adapted from the i386
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* and PPC versions by Greg Ungerer (gerg@snapgear.com)
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*
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* Modified:
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*
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* Bugs: Enter bugs at http://blackfin.uclinux.org/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; see the file COPYING.
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* If not, write to the Free Software Foundation,
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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#ifndef _BLACKFIN_CACHEFLUSH_H
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#define _BLACKFIN_CACHEFLUSH_H
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#include <asm/blackfin.h> /* for SSYNC() */
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extern void blackfin_icache_flush_range(unsigned long start_address, unsigned long end_address);
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extern void blackfin_dcache_flush_range(unsigned long start_address, unsigned long end_address);
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extern void blackfin_dcache_invalidate_range(unsigned long start_address, unsigned long end_address);
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extern void blackfin_dflush_page(void *page);
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extern void blackfin_invalidate_entire_dcache(void);
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extern void blackfin_invalidate_entire_icache(void);
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#define flush_dcache_mmap_lock(mapping) do { } while (0)
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#define flush_dcache_mmap_unlock(mapping) do { } while (0)
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#define flush_cache_mm(mm) do { } while (0)
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#define flush_cache_range(vma, start, end) do { } while (0)
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#define flush_cache_page(vma, vmaddr) do { } while (0)
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#define flush_cache_vmap(start, end) do { } while (0)
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#define flush_cache_vunmap(start, end) do { } while (0)
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#ifdef CONFIG_SMP
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#define flush_icache_range_others(start, end) \
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smp_icache_flush_range_others((start), (end))
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#else
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#define flush_icache_range_others(start, end) do { } while (0)
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#endif
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static inline void flush_icache_range(unsigned start, unsigned end)
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{
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#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK)
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blackfin_dcache_flush_range(start, end);
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#endif
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/* Make sure all write buffers in the data side of the core
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* are flushed before trying to invalidate the icache. This
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* needs to be after the data flush and before the icache
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* flush so that the SSYNC does the right thing in preventing
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* the instruction prefetcher from hitting things in cached
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* memory at the wrong time -- it runs much further ahead than
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* the pipeline.
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*/
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SSYNC();
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#if defined(CONFIG_BFIN_ICACHE)
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blackfin_icache_flush_range(start, end);
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flush_icache_range_others(start, end);
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#endif
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}
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#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
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do { memcpy(dst, src, len); \
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flush_icache_range((unsigned) (dst), (unsigned) (dst) + (len)); \
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} while (0)
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#define copy_from_user_page(vma, page, vaddr, dst, src, len) memcpy(dst, src, len)
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#if defined(CONFIG_BFIN_DCACHE)
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# define invalidate_dcache_range(start,end) blackfin_dcache_invalidate_range((start), (end))
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#else
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# define invalidate_dcache_range(start,end) do { } while (0)
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#endif
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#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK)
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# define flush_dcache_range(start,end) blackfin_dcache_flush_range((start), (end))
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# define flush_dcache_page(page) blackfin_dflush_page(page_address(page))
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#else
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# define flush_dcache_range(start,end) do { } while (0)
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# define flush_dcache_page(page) do { } while (0)
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#endif
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extern unsigned long reserved_mem_dcache_on;
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extern unsigned long reserved_mem_icache_on;
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static inline int bfin_addr_dcacheable(unsigned long addr)
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{
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#ifdef CONFIG_BFIN_EXTMEM_DCACHEABLE
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if (addr < (_ramend - DMA_UNCACHED_REGION))
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return 1;
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#endif
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if (reserved_mem_dcache_on &&
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addr >= _ramend && addr < physical_mem_end)
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return 1;
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#ifdef CONFIG_BFIN_L2_DCACHEABLE
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if (addr >= L2_START && addr < L2_START + L2_LENGTH)
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return 1;
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#endif
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return 0;
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}
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#endif /* _BLACKFIN_ICACHEFLUSH_H */
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