3ba9e10a6d
DAI type information is only ever used within ASoC in order to special case AC97 and for diagnostic purposes. Since modern CPUs and codecs support multi function DAIs which can be configured for several modes it is more trouble than it's worth to maintain anything other than a flag identifying AC97 DAIs so remove the type field and replace it with an ac97_control flag. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
922 lines
22 KiB
C
922 lines
22 KiB
C
#define DEBUG
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/*
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* pxa-ssp.c -- ALSA Soc Audio Layer
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*
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* Copyright 2005,2008 Wolfson Microelectronics PLC.
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* Author: Liam Girdwood
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* Mark Brown <broonie@opensource.wolfsonmicro.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* TODO:
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* o Test network mode for > 16bit sample size
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <sound/core.h>
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#include <sound/pcm.h>
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#include <sound/initval.h>
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#include <sound/pcm_params.h>
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#include <sound/soc.h>
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#include <sound/pxa2xx-lib.h>
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#include <mach/hardware.h>
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#include <mach/pxa-regs.h>
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#include <mach/regs-ssp.h>
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#include <mach/audio.h>
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#include <mach/ssp.h>
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#include "pxa2xx-pcm.h"
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#include "pxa-ssp.h"
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/*
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* SSP audio private data
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*/
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struct ssp_priv {
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struct ssp_dev dev;
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unsigned int sysclk;
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int dai_fmt;
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#ifdef CONFIG_PM
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struct ssp_state state;
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#endif
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};
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#define PXA2xx_SSP1_BASE 0x41000000
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#define PXA27x_SSP2_BASE 0x41700000
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#define PXA27x_SSP3_BASE 0x41900000
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#define PXA3xx_SSP4_BASE 0x41a00000
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static struct pxa2xx_pcm_dma_params pxa_ssp1_pcm_mono_out = {
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.name = "SSP1 PCM Mono out",
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.dev_addr = PXA2xx_SSP1_BASE + SSDR,
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.drcmr = &DRCMR(14),
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.dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG |
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DCMD_BURST16 | DCMD_WIDTH2,
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};
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static struct pxa2xx_pcm_dma_params pxa_ssp1_pcm_mono_in = {
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.name = "SSP1 PCM Mono in",
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.dev_addr = PXA2xx_SSP1_BASE + SSDR,
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.drcmr = &DRCMR(13),
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.dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC |
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DCMD_BURST16 | DCMD_WIDTH2,
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};
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static struct pxa2xx_pcm_dma_params pxa_ssp1_pcm_stereo_out = {
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.name = "SSP1 PCM Stereo out",
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.dev_addr = PXA2xx_SSP1_BASE + SSDR,
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.drcmr = &DRCMR(14),
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.dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG |
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DCMD_BURST16 | DCMD_WIDTH4,
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};
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static struct pxa2xx_pcm_dma_params pxa_ssp1_pcm_stereo_in = {
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.name = "SSP1 PCM Stereo in",
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.dev_addr = PXA2xx_SSP1_BASE + SSDR,
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.drcmr = &DRCMR(13),
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.dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC |
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DCMD_BURST16 | DCMD_WIDTH4,
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};
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static struct pxa2xx_pcm_dma_params pxa_ssp2_pcm_mono_out = {
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.name = "SSP2 PCM Mono out",
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.dev_addr = PXA27x_SSP2_BASE + SSDR,
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.drcmr = &DRCMR(16),
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.dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG |
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DCMD_BURST16 | DCMD_WIDTH2,
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};
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static struct pxa2xx_pcm_dma_params pxa_ssp2_pcm_mono_in = {
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.name = "SSP2 PCM Mono in",
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.dev_addr = PXA27x_SSP2_BASE + SSDR,
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.drcmr = &DRCMR(15),
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.dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC |
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DCMD_BURST16 | DCMD_WIDTH2,
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};
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static struct pxa2xx_pcm_dma_params pxa_ssp2_pcm_stereo_out = {
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.name = "SSP2 PCM Stereo out",
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.dev_addr = PXA27x_SSP2_BASE + SSDR,
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.drcmr = &DRCMR(16),
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.dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG |
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DCMD_BURST16 | DCMD_WIDTH4,
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};
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static struct pxa2xx_pcm_dma_params pxa_ssp2_pcm_stereo_in = {
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.name = "SSP2 PCM Stereo in",
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.dev_addr = PXA27x_SSP2_BASE + SSDR,
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.drcmr = &DRCMR(15),
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.dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC |
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DCMD_BURST16 | DCMD_WIDTH4,
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};
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static struct pxa2xx_pcm_dma_params pxa_ssp3_pcm_mono_out = {
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.name = "SSP3 PCM Mono out",
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.dev_addr = PXA27x_SSP3_BASE + SSDR,
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.drcmr = &DRCMR(67),
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.dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG |
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DCMD_BURST16 | DCMD_WIDTH2,
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};
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static struct pxa2xx_pcm_dma_params pxa_ssp3_pcm_mono_in = {
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.name = "SSP3 PCM Mono in",
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.dev_addr = PXA27x_SSP3_BASE + SSDR,
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.drcmr = &DRCMR(66),
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.dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC |
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DCMD_BURST16 | DCMD_WIDTH2,
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};
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static struct pxa2xx_pcm_dma_params pxa_ssp3_pcm_stereo_out = {
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.name = "SSP3 PCM Stereo out",
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.dev_addr = PXA27x_SSP3_BASE + SSDR,
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.drcmr = &DRCMR(67),
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.dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG |
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DCMD_BURST16 | DCMD_WIDTH4,
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};
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static struct pxa2xx_pcm_dma_params pxa_ssp3_pcm_stereo_in = {
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.name = "SSP3 PCM Stereo in",
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.dev_addr = PXA27x_SSP3_BASE + SSDR,
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.drcmr = &DRCMR(66),
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.dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC |
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DCMD_BURST16 | DCMD_WIDTH4,
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};
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static struct pxa2xx_pcm_dma_params pxa_ssp4_pcm_mono_out = {
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.name = "SSP4 PCM Mono out",
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.dev_addr = PXA3xx_SSP4_BASE + SSDR,
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.drcmr = &DRCMR(67),
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.dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG |
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DCMD_BURST16 | DCMD_WIDTH2,
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};
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static struct pxa2xx_pcm_dma_params pxa_ssp4_pcm_mono_in = {
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.name = "SSP4 PCM Mono in",
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.dev_addr = PXA3xx_SSP4_BASE + SSDR,
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.drcmr = &DRCMR(66),
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.dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC |
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DCMD_BURST16 | DCMD_WIDTH2,
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};
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static struct pxa2xx_pcm_dma_params pxa_ssp4_pcm_stereo_out = {
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.name = "SSP4 PCM Stereo out",
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.dev_addr = PXA3xx_SSP4_BASE + SSDR,
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.drcmr = &DRCMR(67),
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.dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG |
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DCMD_BURST16 | DCMD_WIDTH4,
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};
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static struct pxa2xx_pcm_dma_params pxa_ssp4_pcm_stereo_in = {
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.name = "SSP4 PCM Stereo in",
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.dev_addr = PXA3xx_SSP4_BASE + SSDR,
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.drcmr = &DRCMR(66),
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.dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC |
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DCMD_BURST16 | DCMD_WIDTH4,
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};
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static void dump_registers(struct ssp_device *ssp)
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{
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dev_dbg(&ssp->pdev->dev, "SSCR0 0x%08x SSCR1 0x%08x SSTO 0x%08x\n",
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ssp_read_reg(ssp, SSCR0), ssp_read_reg(ssp, SSCR1),
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ssp_read_reg(ssp, SSTO));
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dev_dbg(&ssp->pdev->dev, "SSPSP 0x%08x SSSR 0x%08x SSACD 0x%08x\n",
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ssp_read_reg(ssp, SSPSP), ssp_read_reg(ssp, SSSR),
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ssp_read_reg(ssp, SSACD));
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}
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static struct pxa2xx_pcm_dma_params *ssp_dma_params[4][4] = {
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{
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&pxa_ssp1_pcm_mono_out, &pxa_ssp1_pcm_mono_in,
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&pxa_ssp1_pcm_stereo_out, &pxa_ssp1_pcm_stereo_in,
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},
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{
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&pxa_ssp2_pcm_mono_out, &pxa_ssp2_pcm_mono_in,
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&pxa_ssp2_pcm_stereo_out, &pxa_ssp2_pcm_stereo_in,
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},
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{
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&pxa_ssp3_pcm_mono_out, &pxa_ssp3_pcm_mono_in,
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&pxa_ssp3_pcm_stereo_out, &pxa_ssp3_pcm_stereo_in,
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},
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{
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&pxa_ssp4_pcm_mono_out, &pxa_ssp4_pcm_mono_in,
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&pxa_ssp4_pcm_stereo_out, &pxa_ssp4_pcm_stereo_in,
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},
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};
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static int pxa_ssp_startup(struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai)
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{
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struct snd_soc_pcm_runtime *rtd = substream->private_data;
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struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
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struct ssp_priv *priv = cpu_dai->private_data;
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int ret = 0;
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if (!cpu_dai->active) {
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ret = ssp_init(&priv->dev, cpu_dai->id + 1, SSP_NO_IRQ);
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if (ret < 0)
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return ret;
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ssp_disable(&priv->dev);
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}
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return ret;
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}
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static void pxa_ssp_shutdown(struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai)
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{
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struct snd_soc_pcm_runtime *rtd = substream->private_data;
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struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
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struct ssp_priv *priv = cpu_dai->private_data;
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if (!cpu_dai->active) {
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ssp_disable(&priv->dev);
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ssp_exit(&priv->dev);
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}
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}
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#ifdef CONFIG_PM
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static int pxa_ssp_suspend(struct platform_device *pdev,
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struct snd_soc_dai *cpu_dai)
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{
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struct ssp_priv *priv = cpu_dai->private_data;
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if (!cpu_dai->active)
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return 0;
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ssp_save_state(&priv->dev, &priv->state);
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clk_disable(priv->dev.ssp->clk);
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return 0;
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}
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static int pxa_ssp_resume(struct platform_device *pdev,
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struct snd_soc_dai *cpu_dai)
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{
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struct ssp_priv *priv = cpu_dai->private_data;
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if (!cpu_dai->active)
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return 0;
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clk_enable(priv->dev.ssp->clk);
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ssp_restore_state(&priv->dev, &priv->state);
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ssp_enable(&priv->dev);
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return 0;
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}
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#else
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#define pxa_ssp_suspend NULL
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#define pxa_ssp_resume NULL
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#endif
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/**
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* ssp_set_clkdiv - set SSP clock divider
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* @div: serial clock rate divider
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*/
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static void ssp_set_scr(struct ssp_dev *dev, u32 div)
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{
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struct ssp_device *ssp = dev->ssp;
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u32 sscr0 = ssp_read_reg(dev->ssp, SSCR0) & ~SSCR0_SCR;
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ssp_write_reg(ssp, SSCR0, (sscr0 | SSCR0_SerClkDiv(div)));
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}
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/*
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* Set the SSP ports SYSCLK.
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*/
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static int pxa_ssp_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
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int clk_id, unsigned int freq, int dir)
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{
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struct ssp_priv *priv = cpu_dai->private_data;
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struct ssp_device *ssp = priv->dev.ssp;
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int val;
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u32 sscr0 = ssp_read_reg(ssp, SSCR0) &
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~(SSCR0_ECS | SSCR0_NCS | SSCR0_MOD | SSCR0_ADC);
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dev_dbg(&ssp->pdev->dev,
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"pxa_ssp_set_dai_sysclk id: %d, clk_id %d, freq %d\n",
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cpu_dai->id, clk_id, freq);
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switch (clk_id) {
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case PXA_SSP_CLK_NET_PLL:
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sscr0 |= SSCR0_MOD;
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break;
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case PXA_SSP_CLK_PLL:
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/* Internal PLL is fixed */
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if (cpu_is_pxa25x())
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priv->sysclk = 1843200;
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else
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priv->sysclk = 13000000;
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break;
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case PXA_SSP_CLK_EXT:
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priv->sysclk = freq;
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sscr0 |= SSCR0_ECS;
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break;
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case PXA_SSP_CLK_NET:
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priv->sysclk = freq;
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sscr0 |= SSCR0_NCS | SSCR0_MOD;
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break;
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case PXA_SSP_CLK_AUDIO:
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priv->sysclk = 0;
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ssp_set_scr(&priv->dev, 1);
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sscr0 |= SSCR0_ADC;
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break;
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default:
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return -ENODEV;
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}
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/* The SSP clock must be disabled when changing SSP clock mode
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* on PXA2xx. On PXA3xx it must be enabled when doing so. */
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if (!cpu_is_pxa3xx())
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clk_disable(priv->dev.ssp->clk);
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val = ssp_read_reg(ssp, SSCR0) | sscr0;
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ssp_write_reg(ssp, SSCR0, val);
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if (!cpu_is_pxa3xx())
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clk_enable(priv->dev.ssp->clk);
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return 0;
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}
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/*
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* Set the SSP clock dividers.
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*/
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static int pxa_ssp_set_dai_clkdiv(struct snd_soc_dai *cpu_dai,
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int div_id, int div)
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{
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struct ssp_priv *priv = cpu_dai->private_data;
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struct ssp_device *ssp = priv->dev.ssp;
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int val;
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switch (div_id) {
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case PXA_SSP_AUDIO_DIV_ACDS:
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val = (ssp_read_reg(ssp, SSACD) & ~0x7) | SSACD_ACDS(div);
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ssp_write_reg(ssp, SSACD, val);
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break;
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case PXA_SSP_AUDIO_DIV_SCDB:
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val = ssp_read_reg(ssp, SSACD);
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val &= ~SSACD_SCDB;
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#if defined(CONFIG_PXA3xx)
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if (cpu_is_pxa3xx())
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val &= ~SSACD_SCDX8;
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#endif
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switch (div) {
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case PXA_SSP_CLK_SCDB_1:
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val |= SSACD_SCDB;
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break;
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case PXA_SSP_CLK_SCDB_4:
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break;
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#if defined(CONFIG_PXA3xx)
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case PXA_SSP_CLK_SCDB_8:
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if (cpu_is_pxa3xx())
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val |= SSACD_SCDX8;
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else
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return -EINVAL;
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break;
|
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#endif
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default:
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return -EINVAL;
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}
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ssp_write_reg(ssp, SSACD, val);
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break;
|
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case PXA_SSP_DIV_SCR:
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ssp_set_scr(&priv->dev, div);
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break;
|
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default:
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return -ENODEV;
|
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}
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|
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return 0;
|
|
}
|
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|
|
/*
|
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* Configure the PLL frequency pxa27x and (afaik - pxa320 only)
|
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*/
|
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static int pxa_ssp_set_dai_pll(struct snd_soc_dai *cpu_dai,
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int pll_id, unsigned int freq_in, unsigned int freq_out)
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{
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struct ssp_priv *priv = cpu_dai->private_data;
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struct ssp_device *ssp = priv->dev.ssp;
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u32 ssacd = ssp_read_reg(ssp, SSACD) & ~0x70;
|
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|
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#if defined(CONFIG_PXA3xx)
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if (cpu_is_pxa3xx())
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ssp_write_reg(ssp, SSACDD, 0);
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#endif
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|
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switch (freq_out) {
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case 5622000:
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break;
|
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case 11345000:
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ssacd |= (0x1 << 4);
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break;
|
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case 12235000:
|
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ssacd |= (0x2 << 4);
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break;
|
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case 14857000:
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ssacd |= (0x3 << 4);
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break;
|
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case 32842000:
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ssacd |= (0x4 << 4);
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break;
|
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case 48000000:
|
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ssacd |= (0x5 << 4);
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break;
|
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case 0:
|
|
/* Disable */
|
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break;
|
|
|
|
default:
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#ifdef CONFIG_PXA3xx
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|
/* PXA3xx has a clock ditherer which can be used to generate
|
|
* a wider range of frequencies - calculate a value for it.
|
|
*/
|
|
if (cpu_is_pxa3xx()) {
|
|
u32 val;
|
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u64 tmp = 19968;
|
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tmp *= 1000000;
|
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do_div(tmp, freq_out);
|
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val = tmp;
|
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|
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val = (val << 16) | 64;;
|
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ssp_write_reg(ssp, SSACDD, val);
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|
|
ssacd |= (0x6 << 4);
|
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|
|
dev_dbg(&ssp->pdev->dev,
|
|
"Using SSACDD %x to supply %dHz\n",
|
|
val, freq_out);
|
|
break;
|
|
}
|
|
#endif
|
|
|
|
return -EINVAL;
|
|
}
|
|
|
|
ssp_write_reg(ssp, SSACD, ssacd);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Set the active slots in TDM/Network mode
|
|
*/
|
|
static int pxa_ssp_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai,
|
|
unsigned int mask, int slots)
|
|
{
|
|
struct ssp_priv *priv = cpu_dai->private_data;
|
|
struct ssp_device *ssp = priv->dev.ssp;
|
|
u32 sscr0;
|
|
|
|
sscr0 = ssp_read_reg(ssp, SSCR0) & ~SSCR0_SlotsPerFrm(7);
|
|
|
|
/* set number of active slots */
|
|
sscr0 |= SSCR0_SlotsPerFrm(slots);
|
|
ssp_write_reg(ssp, SSCR0, sscr0);
|
|
|
|
/* set active slot mask */
|
|
ssp_write_reg(ssp, SSTSA, mask);
|
|
ssp_write_reg(ssp, SSRSA, mask);
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Tristate the SSP DAI lines
|
|
*/
|
|
static int pxa_ssp_set_dai_tristate(struct snd_soc_dai *cpu_dai,
|
|
int tristate)
|
|
{
|
|
struct ssp_priv *priv = cpu_dai->private_data;
|
|
struct ssp_device *ssp = priv->dev.ssp;
|
|
u32 sscr1;
|
|
|
|
sscr1 = ssp_read_reg(ssp, SSCR1);
|
|
if (tristate)
|
|
sscr1 &= ~SSCR1_TTE;
|
|
else
|
|
sscr1 |= SSCR1_TTE;
|
|
ssp_write_reg(ssp, SSCR1, sscr1);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Set up the SSP DAI format.
|
|
* The SSP Port must be inactive before calling this function as the
|
|
* physical interface format is changed.
|
|
*/
|
|
static int pxa_ssp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
|
|
unsigned int fmt)
|
|
{
|
|
struct ssp_priv *priv = cpu_dai->private_data;
|
|
struct ssp_device *ssp = priv->dev.ssp;
|
|
u32 sscr0;
|
|
u32 sscr1;
|
|
u32 sspsp;
|
|
|
|
/* reset port settings */
|
|
sscr0 = ssp_read_reg(ssp, SSCR0) &
|
|
(SSCR0_ECS | SSCR0_NCS | SSCR0_MOD | SSCR0_ADC);
|
|
sscr1 = SSCR1_RxTresh(8) | SSCR1_TxTresh(7);
|
|
sspsp = 0;
|
|
|
|
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
|
|
case SND_SOC_DAIFMT_CBM_CFM:
|
|
sscr1 |= SSCR1_SCLKDIR | SSCR1_SFRMDIR;
|
|
break;
|
|
case SND_SOC_DAIFMT_CBM_CFS:
|
|
sscr1 |= SSCR1_SCLKDIR;
|
|
break;
|
|
case SND_SOC_DAIFMT_CBS_CFS:
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
ssp_write_reg(ssp, SSCR0, sscr0);
|
|
ssp_write_reg(ssp, SSCR1, sscr1);
|
|
ssp_write_reg(ssp, SSPSP, sspsp);
|
|
|
|
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
|
|
case SND_SOC_DAIFMT_I2S:
|
|
sscr0 |= SSCR0_MOD | SSCR0_PSP;
|
|
sscr1 |= SSCR1_RWOT | SSCR1_TRAIL;
|
|
|
|
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
|
|
case SND_SOC_DAIFMT_NB_NF:
|
|
sspsp |= SSPSP_FSRT;
|
|
break;
|
|
case SND_SOC_DAIFMT_NB_IF:
|
|
sspsp |= SSPSP_SFRMP | SSPSP_FSRT;
|
|
break;
|
|
case SND_SOC_DAIFMT_IB_IF:
|
|
sspsp |= SSPSP_SFRMP;
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
break;
|
|
|
|
case SND_SOC_DAIFMT_DSP_A:
|
|
sspsp |= SSPSP_FSRT;
|
|
case SND_SOC_DAIFMT_DSP_B:
|
|
sscr0 |= SSCR0_MOD | SSCR0_PSP;
|
|
sscr1 |= SSCR1_TRAIL | SSCR1_RWOT;
|
|
|
|
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
|
|
case SND_SOC_DAIFMT_NB_NF:
|
|
sspsp |= SSPSP_SFRMP;
|
|
break;
|
|
case SND_SOC_DAIFMT_IB_IF:
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
break;
|
|
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
ssp_write_reg(ssp, SSCR0, sscr0);
|
|
ssp_write_reg(ssp, SSCR1, sscr1);
|
|
ssp_write_reg(ssp, SSPSP, sspsp);
|
|
|
|
dump_registers(ssp);
|
|
|
|
/* Since we are configuring the timings for the format by hand
|
|
* we have to defer some things until hw_params() where we
|
|
* know parameters like the sample size.
|
|
*/
|
|
priv->dai_fmt = fmt;
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Set the SSP audio DMA parameters and sample size.
|
|
* Can be called multiple times by oss emulation.
|
|
*/
|
|
static int pxa_ssp_hw_params(struct snd_pcm_substream *substream,
|
|
struct snd_pcm_hw_params *params,
|
|
struct snd_soc_dai *dai)
|
|
{
|
|
struct snd_soc_pcm_runtime *rtd = substream->private_data;
|
|
struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
|
|
struct ssp_priv *priv = cpu_dai->private_data;
|
|
struct ssp_device *ssp = priv->dev.ssp;
|
|
int dma = 0, chn = params_channels(params);
|
|
u32 sscr0;
|
|
u32 sspsp;
|
|
int width = snd_pcm_format_physical_width(params_format(params));
|
|
|
|
/* select correct DMA params */
|
|
if (substream->stream != SNDRV_PCM_STREAM_PLAYBACK)
|
|
dma = 1; /* capture DMA offset is 1,3 */
|
|
if (chn == 2)
|
|
dma += 2; /* stereo DMA offset is 2, mono is 0 */
|
|
cpu_dai->dma_data = ssp_dma_params[cpu_dai->id][dma];
|
|
|
|
dev_dbg(&ssp->pdev->dev, "pxa_ssp_hw_params: dma %d\n", dma);
|
|
|
|
/* we can only change the settings if the port is not in use */
|
|
if (ssp_read_reg(ssp, SSCR0) & SSCR0_SSE)
|
|
return 0;
|
|
|
|
/* clear selected SSP bits */
|
|
sscr0 = ssp_read_reg(ssp, SSCR0) & ~(SSCR0_DSS | SSCR0_EDSS);
|
|
ssp_write_reg(ssp, SSCR0, sscr0);
|
|
|
|
/* bit size */
|
|
sscr0 = ssp_read_reg(ssp, SSCR0);
|
|
switch (params_format(params)) {
|
|
case SNDRV_PCM_FORMAT_S16_LE:
|
|
#ifdef CONFIG_PXA3xx
|
|
if (cpu_is_pxa3xx())
|
|
sscr0 |= SSCR0_FPCKE;
|
|
#endif
|
|
sscr0 |= SSCR0_DataSize(16);
|
|
if (params_channels(params) > 1)
|
|
sscr0 |= SSCR0_EDSS;
|
|
break;
|
|
case SNDRV_PCM_FORMAT_S24_LE:
|
|
sscr0 |= (SSCR0_EDSS | SSCR0_DataSize(8));
|
|
/* we must be in network mode (2 slots) for 24 bit stereo */
|
|
break;
|
|
case SNDRV_PCM_FORMAT_S32_LE:
|
|
sscr0 |= (SSCR0_EDSS | SSCR0_DataSize(16));
|
|
/* we must be in network mode (2 slots) for 32 bit stereo */
|
|
break;
|
|
}
|
|
ssp_write_reg(ssp, SSCR0, sscr0);
|
|
|
|
switch (priv->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
|
|
case SND_SOC_DAIFMT_I2S:
|
|
/* Cleared when the DAI format is set */
|
|
sspsp = ssp_read_reg(ssp, SSPSP) | SSPSP_SFRMWDTH(width);
|
|
ssp_write_reg(ssp, SSPSP, sspsp);
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
/* We always use a network mode so we always require TDM slots
|
|
* - complain loudly and fail if they've not been set up yet.
|
|
*/
|
|
if (!(ssp_read_reg(ssp, SSTSA) & 0xf)) {
|
|
dev_err(&ssp->pdev->dev, "No TDM timeslot configured\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
dump_registers(ssp);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int pxa_ssp_trigger(struct snd_pcm_substream *substream, int cmd,
|
|
struct snd_soc_dai *dai)
|
|
{
|
|
struct snd_soc_pcm_runtime *rtd = substream->private_data;
|
|
struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
|
|
int ret = 0;
|
|
struct ssp_priv *priv = cpu_dai->private_data;
|
|
struct ssp_device *ssp = priv->dev.ssp;
|
|
int val;
|
|
|
|
switch (cmd) {
|
|
case SNDRV_PCM_TRIGGER_RESUME:
|
|
ssp_enable(&priv->dev);
|
|
break;
|
|
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
|
|
val = ssp_read_reg(ssp, SSCR1);
|
|
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
|
|
val |= SSCR1_TSRE;
|
|
else
|
|
val |= SSCR1_RSRE;
|
|
ssp_write_reg(ssp, SSCR1, val);
|
|
val = ssp_read_reg(ssp, SSSR);
|
|
ssp_write_reg(ssp, SSSR, val);
|
|
break;
|
|
case SNDRV_PCM_TRIGGER_START:
|
|
val = ssp_read_reg(ssp, SSCR1);
|
|
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
|
|
val |= SSCR1_TSRE;
|
|
else
|
|
val |= SSCR1_RSRE;
|
|
ssp_write_reg(ssp, SSCR1, val);
|
|
ssp_enable(&priv->dev);
|
|
break;
|
|
case SNDRV_PCM_TRIGGER_STOP:
|
|
val = ssp_read_reg(ssp, SSCR1);
|
|
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
|
|
val &= ~SSCR1_TSRE;
|
|
else
|
|
val &= ~SSCR1_RSRE;
|
|
ssp_write_reg(ssp, SSCR1, val);
|
|
break;
|
|
case SNDRV_PCM_TRIGGER_SUSPEND:
|
|
ssp_disable(&priv->dev);
|
|
break;
|
|
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
|
|
val = ssp_read_reg(ssp, SSCR1);
|
|
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
|
|
val &= ~SSCR1_TSRE;
|
|
else
|
|
val &= ~SSCR1_RSRE;
|
|
ssp_write_reg(ssp, SSCR1, val);
|
|
break;
|
|
|
|
default:
|
|
ret = -EINVAL;
|
|
}
|
|
|
|
dump_registers(ssp);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int pxa_ssp_probe(struct platform_device *pdev,
|
|
struct snd_soc_dai *dai)
|
|
{
|
|
struct ssp_priv *priv;
|
|
int ret;
|
|
|
|
priv = kzalloc(sizeof(struct ssp_priv), GFP_KERNEL);
|
|
if (!priv)
|
|
return -ENOMEM;
|
|
|
|
priv->dev.ssp = ssp_request(dai->id, "SoC audio");
|
|
if (priv->dev.ssp == NULL) {
|
|
ret = -ENODEV;
|
|
goto err_priv;
|
|
}
|
|
|
|
dai->private_data = priv;
|
|
|
|
return 0;
|
|
|
|
err_priv:
|
|
kfree(priv);
|
|
return ret;
|
|
}
|
|
|
|
static void pxa_ssp_remove(struct platform_device *pdev,
|
|
struct snd_soc_dai *dai)
|
|
{
|
|
struct ssp_priv *priv = dai->private_data;
|
|
ssp_free(priv->dev.ssp);
|
|
}
|
|
|
|
#define PXA_SSP_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
|
|
SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | \
|
|
SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 | \
|
|
SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
|
|
|
|
#define PXA_SSP_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
|
|
SNDRV_PCM_FMTBIT_S24_LE | \
|
|
SNDRV_PCM_FMTBIT_S32_LE)
|
|
|
|
struct snd_soc_dai pxa_ssp_dai[] = {
|
|
{
|
|
.name = "pxa2xx-ssp1",
|
|
.id = 0,
|
|
.probe = pxa_ssp_probe,
|
|
.remove = pxa_ssp_remove,
|
|
.suspend = pxa_ssp_suspend,
|
|
.resume = pxa_ssp_resume,
|
|
.playback = {
|
|
.channels_min = 1,
|
|
.channels_max = 2,
|
|
.rates = PXA_SSP_RATES,
|
|
.formats = PXA_SSP_FORMATS,
|
|
},
|
|
.capture = {
|
|
.channels_min = 1,
|
|
.channels_max = 2,
|
|
.rates = PXA_SSP_RATES,
|
|
.formats = PXA_SSP_FORMATS,
|
|
},
|
|
.ops = {
|
|
.startup = pxa_ssp_startup,
|
|
.shutdown = pxa_ssp_shutdown,
|
|
.trigger = pxa_ssp_trigger,
|
|
.hw_params = pxa_ssp_hw_params,
|
|
.set_sysclk = pxa_ssp_set_dai_sysclk,
|
|
.set_clkdiv = pxa_ssp_set_dai_clkdiv,
|
|
.set_pll = pxa_ssp_set_dai_pll,
|
|
.set_fmt = pxa_ssp_set_dai_fmt,
|
|
.set_tdm_slot = pxa_ssp_set_dai_tdm_slot,
|
|
.set_tristate = pxa_ssp_set_dai_tristate,
|
|
},
|
|
},
|
|
{ .name = "pxa2xx-ssp2",
|
|
.id = 1,
|
|
.probe = pxa_ssp_probe,
|
|
.remove = pxa_ssp_remove,
|
|
.suspend = pxa_ssp_suspend,
|
|
.resume = pxa_ssp_resume,
|
|
.playback = {
|
|
.channels_min = 1,
|
|
.channels_max = 2,
|
|
.rates = PXA_SSP_RATES,
|
|
.formats = PXA_SSP_FORMATS,
|
|
},
|
|
.capture = {
|
|
.channels_min = 1,
|
|
.channels_max = 2,
|
|
.rates = PXA_SSP_RATES,
|
|
.formats = PXA_SSP_FORMATS,
|
|
},
|
|
.ops = {
|
|
.startup = pxa_ssp_startup,
|
|
.shutdown = pxa_ssp_shutdown,
|
|
.trigger = pxa_ssp_trigger,
|
|
.hw_params = pxa_ssp_hw_params,
|
|
.set_sysclk = pxa_ssp_set_dai_sysclk,
|
|
.set_clkdiv = pxa_ssp_set_dai_clkdiv,
|
|
.set_pll = pxa_ssp_set_dai_pll,
|
|
.set_fmt = pxa_ssp_set_dai_fmt,
|
|
.set_tdm_slot = pxa_ssp_set_dai_tdm_slot,
|
|
.set_tristate = pxa_ssp_set_dai_tristate,
|
|
},
|
|
},
|
|
{
|
|
.name = "pxa2xx-ssp3",
|
|
.id = 2,
|
|
.probe = pxa_ssp_probe,
|
|
.remove = pxa_ssp_remove,
|
|
.suspend = pxa_ssp_suspend,
|
|
.resume = pxa_ssp_resume,
|
|
.playback = {
|
|
.channels_min = 1,
|
|
.channels_max = 2,
|
|
.rates = PXA_SSP_RATES,
|
|
.formats = PXA_SSP_FORMATS,
|
|
},
|
|
.capture = {
|
|
.channels_min = 1,
|
|
.channels_max = 2,
|
|
.rates = PXA_SSP_RATES,
|
|
.formats = PXA_SSP_FORMATS,
|
|
},
|
|
.ops = {
|
|
.startup = pxa_ssp_startup,
|
|
.shutdown = pxa_ssp_shutdown,
|
|
.trigger = pxa_ssp_trigger,
|
|
.hw_params = pxa_ssp_hw_params,
|
|
.set_sysclk = pxa_ssp_set_dai_sysclk,
|
|
.set_clkdiv = pxa_ssp_set_dai_clkdiv,
|
|
.set_pll = pxa_ssp_set_dai_pll,
|
|
.set_fmt = pxa_ssp_set_dai_fmt,
|
|
.set_tdm_slot = pxa_ssp_set_dai_tdm_slot,
|
|
.set_tristate = pxa_ssp_set_dai_tristate,
|
|
},
|
|
},
|
|
{
|
|
.name = "pxa2xx-ssp4",
|
|
.id = 3,
|
|
.probe = pxa_ssp_probe,
|
|
.remove = pxa_ssp_remove,
|
|
.suspend = pxa_ssp_suspend,
|
|
.resume = pxa_ssp_resume,
|
|
.playback = {
|
|
.channels_min = 1,
|
|
.channels_max = 2,
|
|
.rates = PXA_SSP_RATES,
|
|
.formats = PXA_SSP_FORMATS,
|
|
},
|
|
.capture = {
|
|
.channels_min = 1,
|
|
.channels_max = 2,
|
|
.rates = PXA_SSP_RATES,
|
|
.formats = PXA_SSP_FORMATS,
|
|
},
|
|
.ops = {
|
|
.startup = pxa_ssp_startup,
|
|
.shutdown = pxa_ssp_shutdown,
|
|
.trigger = pxa_ssp_trigger,
|
|
.hw_params = pxa_ssp_hw_params,
|
|
.set_sysclk = pxa_ssp_set_dai_sysclk,
|
|
.set_clkdiv = pxa_ssp_set_dai_clkdiv,
|
|
.set_pll = pxa_ssp_set_dai_pll,
|
|
.set_fmt = pxa_ssp_set_dai_fmt,
|
|
.set_tdm_slot = pxa_ssp_set_dai_tdm_slot,
|
|
.set_tristate = pxa_ssp_set_dai_tristate,
|
|
},
|
|
},
|
|
};
|
|
EXPORT_SYMBOL_GPL(pxa_ssp_dai);
|
|
|
|
/* Module information */
|
|
MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
|
|
MODULE_DESCRIPTION("PXA SSP/PCM SoC Interface");
|
|
MODULE_LICENSE("GPL");
|