7271339347
#88: FILE: arch/x86/kernel/cpu/mcheck/k7.c:34: + rdmsr(MSR_IA32_MC0_STATUS+i*4,low, high); ^ ERROR: need space after that ',' (ctx:VxV) #142: FILE: arch/x86/kernel/cpu/mcheck/p4.c:170: + rdmsr(MSR_IA32_MC0_STATUS+i*4,low, high); ^ ERROR: need space after that ',' (ctx:VxV) #180: FILE: arch/x86/kernel/cpu/mcheck/p6.c:34: + rdmsr(MSR_IA32_MC0_STATUS+i*4,low, high); ^ total: 3 errors, 0 warnings, 114 lines checked Your patch has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. Please run checkpatch prior to sending patches Cc: Min Zhang <mzhang@mvista.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
123 lines
3.0 KiB
C
123 lines
3.0 KiB
C
/*
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* P6 specific Machine Check Exception Reporting
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* (C) Copyright 2002 Alan Cox <alan@redhat.com>
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*/
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#include <linux/init.h>
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/interrupt.h>
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#include <linux/smp.h>
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#include <asm/processor.h>
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#include <asm/system.h>
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#include <asm/msr.h>
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#include "mce.h"
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/* Machine Check Handler For PII/PIII */
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static void intel_machine_check(struct pt_regs * regs, long error_code)
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{
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int recover=1;
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u32 alow, ahigh, high, low;
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u32 mcgstl, mcgsth;
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int i;
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rdmsr (MSR_IA32_MCG_STATUS, mcgstl, mcgsth);
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if (mcgstl & (1<<0)) /* Recoverable ? */
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recover=0;
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printk(KERN_EMERG "CPU %d: Machine Check Exception: %08x%08x\n",
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smp_processor_id(), mcgsth, mcgstl);
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for (i = 0; i < nr_mce_banks; i++) {
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rdmsr(MSR_IA32_MC0_STATUS+i*4, low, high);
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if (high & (1<<31)) {
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char misc[20];
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char addr[24];
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misc[0] = addr[0] = '\0';
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if (high & (1<<29))
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recover |= 1;
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if (high & (1<<25))
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recover |= 2;
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high &= ~(1<<31);
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if (high & (1<<27)) {
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rdmsr(MSR_IA32_MC0_MISC+i*4, alow, ahigh);
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snprintf(misc, 20, "[%08x%08x]", ahigh, alow);
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}
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if (high & (1<<26)) {
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rdmsr(MSR_IA32_MC0_ADDR+i*4, alow, ahigh);
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snprintf(addr, 24, " at %08x%08x", ahigh, alow);
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}
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printk(KERN_EMERG "CPU %d: Bank %d: %08x%08x%s%s\n",
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smp_processor_id(), i, high, low, misc, addr);
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}
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}
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if (recover & 2)
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panic ("CPU context corrupt");
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if (recover & 1)
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panic ("Unable to continue");
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printk (KERN_EMERG "Attempting to continue.\n");
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/*
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* Do not clear the MSR_IA32_MCi_STATUS if the error is not
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* recoverable/continuable.This will allow BIOS to look at the MSRs
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* for errors if the OS could not log the error.
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*/
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for (i=0; i<nr_mce_banks; i++) {
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unsigned int msr;
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msr = MSR_IA32_MC0_STATUS+i*4;
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rdmsr (msr,low, high);
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if (high & (1<<31)) {
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/* Clear it */
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wrmsr (msr, 0UL, 0UL);
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/* Serialize */
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wmb();
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add_taint(TAINT_MACHINE_CHECK);
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}
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}
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mcgstl &= ~(1<<2);
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wrmsr (MSR_IA32_MCG_STATUS,mcgstl, mcgsth);
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}
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/* Set up machine check reporting for processors with Intel style MCE */
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void intel_p6_mcheck_init(struct cpuinfo_x86 *c)
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{
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u32 l, h;
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int i;
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/* Check for MCE support */
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if (!cpu_has(c, X86_FEATURE_MCE))
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return;
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/* Check for PPro style MCA */
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if (!cpu_has(c, X86_FEATURE_MCA))
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return;
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/* Ok machine check is available */
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machine_check_vector = intel_machine_check;
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wmb();
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printk (KERN_INFO "Intel machine check architecture supported.\n");
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rdmsr (MSR_IA32_MCG_CAP, l, h);
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if (l & (1<<8)) /* Control register present ? */
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wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
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nr_mce_banks = l & 0xff;
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/*
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* Following the example in IA-32 SDM Vol 3:
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* - MC0_CTL should not be written
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* - Status registers on all banks should be cleared on reset
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*/
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for (i=1; i<nr_mce_banks; i++)
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wrmsr (MSR_IA32_MC0_CTL+4*i, 0xffffffff, 0xffffffff);
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for (i=0; i<nr_mce_banks; i++)
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wrmsr (MSR_IA32_MC0_STATUS+4*i, 0x0, 0x0);
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set_in_cr4 (X86_CR4_MCE);
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printk (KERN_INFO "Intel machine check reporting enabled on CPU#%d.\n",
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smp_processor_id());
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}
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