4348810a24
Kernel space needs very little in the way of BTC maintanence as most mappings which are created and destroyed are non-executable, and so could never enter the instruction stream. The case which does warrant BTC maintanence is when a module is loaded. This creates a new executable mapping, but at that point the pages have not been initialized with code and data, so at that point they contain unpredictable information. Invalidating the BTC at this stage serves little useful purpose. Before we execute module code, we call flush_icache_range(), which deals with the BTC maintanence requirements. This ensures that we have a BTC maintanence operation before we execute code via the newly created mapping. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
74 lines
1.8 KiB
ArmAsm
74 lines
1.8 KiB
ArmAsm
/*
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* linux/arch/arm/mm/tlb-fa.S
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*
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* Copyright (C) 2005 Faraday Corp.
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* Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
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*
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* Based on tlb-v4wbi.S:
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* Copyright (C) 1997-2002 Russell King
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* ARM architecture version 4, Faraday variation.
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* This assume an unified TLBs, with a write buffer, and branch target buffer (BTB)
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*
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* Processors: FA520 FA526 FA626
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*/
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#include <linux/linkage.h>
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#include <linux/init.h>
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#include <asm/asm-offsets.h>
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#include <asm/tlbflush.h>
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#include "proc-macros.S"
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/*
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* flush_user_tlb_range(start, end, mm)
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*
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* Invalidate a range of TLB entries in the specified address space.
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*
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* - start - range start address
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* - end - range end address
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* - mm - mm_struct describing address space
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*/
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.align 4
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ENTRY(fa_flush_user_tlb_range)
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vma_vm_mm ip, r2
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act_mm r3 @ get current->active_mm
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eors r3, ip, r3 @ == mm ?
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movne pc, lr @ no, we dont do anything
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mov r3, #0
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mcr p15, 0, r3, c7, c10, 4 @ drain WB
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bic r0, r0, #0x0ff
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bic r0, r0, #0xf00
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1: mcr p15, 0, r0, c8, c7, 1 @ invalidate UTLB entry
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add r0, r0, #PAGE_SZ
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cmp r0, r1
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blo 1b
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mcr p15, 0, r3, c7, c10, 4 @ data write barrier
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mov pc, lr
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ENTRY(fa_flush_kern_tlb_range)
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mov r3, #0
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mcr p15, 0, r3, c7, c10, 4 @ drain WB
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bic r0, r0, #0x0ff
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bic r0, r0, #0xf00
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1: mcr p15, 0, r0, c8, c7, 1 @ invalidate UTLB entry
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add r0, r0, #PAGE_SZ
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cmp r0, r1
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blo 1b
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mcr p15, 0, r3, c7, c10, 4 @ data write barrier
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mcr p15, 0, r3, c7, c5, 4 @ prefetch flush (isb)
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mov pc, lr
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__INITDATA
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.type fa_tlb_fns, #object
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ENTRY(fa_tlb_fns)
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.long fa_flush_user_tlb_range
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.long fa_flush_kern_tlb_range
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.long fa_tlb_flags
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.size fa_tlb_fns, . - fa_tlb_fns
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