673dd36f0d
Use the SoC infrastructure to hold the interrupt controller information (i.e., base address, default priorities, interrupt controller type, and the number of IRQs). The interrupt controller base, although initially put in the soc_info structure's intc_base field, is eventually put in the global 'davinci_intc_base' so the low-level interrupt code can access it without a dereference. These changes enable the SoC default irq priorities to be put in the SoC-specific files, and the interrupt controller to be at any base address. Signed-off-by: Mark A. Greer <mgreer@mvista.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
210 lines
6.4 KiB
C
210 lines
6.4 KiB
C
/*
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* DaVinci interrupt controller definitions
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*
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* Copyright (C) 2006 Texas Instruments.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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*/
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#ifndef __ASM_ARCH_IRQS_H
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#define __ASM_ARCH_IRQS_H
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/* Base address */
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#define DAVINCI_ARM_INTC_BASE 0x01C48000
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#define DAVINCI_INTC_TYPE_AINTC 0
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#define DAVINCI_INTC_TYPE_CP_INTC 1
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/* Interrupt lines */
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#define IRQ_VDINT0 0
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#define IRQ_VDINT1 1
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#define IRQ_VDINT2 2
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#define IRQ_HISTINT 3
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#define IRQ_H3AINT 4
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#define IRQ_PRVUINT 5
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#define IRQ_RSZINT 6
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#define IRQ_VFOCINT 7
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#define IRQ_VENCINT 8
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#define IRQ_ASQINT 9
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#define IRQ_IMXINT 10
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#define IRQ_VLCDINT 11
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#define IRQ_USBINT 12
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#define IRQ_EMACINT 13
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#define IRQ_CCINT0 16
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#define IRQ_CCERRINT 17
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#define IRQ_TCERRINT0 18
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#define IRQ_TCERRINT 19
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#define IRQ_PSCIN 20
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#define IRQ_IDE 22
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#define IRQ_HPIINT 23
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#define IRQ_MBXINT 24
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#define IRQ_MBRINT 25
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#define IRQ_MMCINT 26
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#define IRQ_SDIOINT 27
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#define IRQ_MSINT 28
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#define IRQ_DDRINT 29
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#define IRQ_AEMIFINT 30
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#define IRQ_VLQINT 31
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#define IRQ_TINT0_TINT12 32
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#define IRQ_TINT0_TINT34 33
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#define IRQ_TINT1_TINT12 34
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#define IRQ_TINT1_TINT34 35
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#define IRQ_PWMINT0 36
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#define IRQ_PWMINT1 37
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#define IRQ_PWMINT2 38
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#define IRQ_I2C 39
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#define IRQ_UARTINT0 40
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#define IRQ_UARTINT1 41
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#define IRQ_UARTINT2 42
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#define IRQ_SPINT0 43
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#define IRQ_SPINT1 44
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#define IRQ_DSP2ARM0 46
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#define IRQ_DSP2ARM1 47
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#define IRQ_GPIO0 48
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#define IRQ_GPIO1 49
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#define IRQ_GPIO2 50
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#define IRQ_GPIO3 51
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#define IRQ_GPIO4 52
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#define IRQ_GPIO5 53
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#define IRQ_GPIO6 54
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#define IRQ_GPIO7 55
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#define IRQ_GPIOBNK0 56
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#define IRQ_GPIOBNK1 57
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#define IRQ_GPIOBNK2 58
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#define IRQ_GPIOBNK3 59
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#define IRQ_GPIOBNK4 60
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#define IRQ_COMMTX 61
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#define IRQ_COMMRX 62
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#define IRQ_EMUINT 63
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#define DAVINCI_N_AINTC_IRQ 64
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#define DAVINCI_N_GPIO 104
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#define NR_IRQS (DAVINCI_N_AINTC_IRQ + DAVINCI_N_GPIO)
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#define ARCH_TIMER_IRQ IRQ_TINT1_TINT34
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/* DaVinci DM6467-specific Interrupts */
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#define IRQ_DM646X_VP_VERTINT0 0
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#define IRQ_DM646X_VP_VERTINT1 1
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#define IRQ_DM646X_VP_VERTINT2 2
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#define IRQ_DM646X_VP_VERTINT3 3
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#define IRQ_DM646X_VP_ERRINT 4
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#define IRQ_DM646X_RESERVED_1 5
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#define IRQ_DM646X_RESERVED_2 6
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#define IRQ_DM646X_WDINT 7
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#define IRQ_DM646X_CRGENINT0 8
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#define IRQ_DM646X_CRGENINT1 9
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#define IRQ_DM646X_TSIFINT0 10
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#define IRQ_DM646X_TSIFINT1 11
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#define IRQ_DM646X_VDCEINT 12
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#define IRQ_DM646X_USBINT 13
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#define IRQ_DM646X_USBDMAINT 14
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#define IRQ_DM646X_PCIINT 15
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#define IRQ_DM646X_TCERRINT2 20
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#define IRQ_DM646X_TCERRINT3 21
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#define IRQ_DM646X_IDE 22
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#define IRQ_DM646X_HPIINT 23
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#define IRQ_DM646X_EMACRXTHINT 24
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#define IRQ_DM646X_EMACRXINT 25
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#define IRQ_DM646X_EMACTXINT 26
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#define IRQ_DM646X_EMACMISCINT 27
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#define IRQ_DM646X_MCASP0TXINT 28
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#define IRQ_DM646X_MCASP0RXINT 29
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#define IRQ_DM646X_RESERVED_3 31
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#define IRQ_DM646X_MCASP1TXINT 32
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#define IRQ_DM646X_VLQINT 38
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#define IRQ_DM646X_UARTINT2 42
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#define IRQ_DM646X_SPINT0 43
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#define IRQ_DM646X_SPINT1 44
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#define IRQ_DM646X_DSP2ARMINT 45
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#define IRQ_DM646X_RESERVED_4 46
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#define IRQ_DM646X_PSCINT 47
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#define IRQ_DM646X_GPIO0 48
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#define IRQ_DM646X_GPIO1 49
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#define IRQ_DM646X_GPIO2 50
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#define IRQ_DM646X_GPIO3 51
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#define IRQ_DM646X_GPIO4 52
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#define IRQ_DM646X_GPIO5 53
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#define IRQ_DM646X_GPIO6 54
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#define IRQ_DM646X_GPIO7 55
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#define IRQ_DM646X_GPIOBNK0 56
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#define IRQ_DM646X_GPIOBNK1 57
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#define IRQ_DM646X_GPIOBNK2 58
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#define IRQ_DM646X_DDRINT 59
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#define IRQ_DM646X_AEMIFINT 60
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/* DaVinci DM355-specific Interrupts */
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#define IRQ_DM355_CCDC_VDINT0 0
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#define IRQ_DM355_CCDC_VDINT1 1
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#define IRQ_DM355_CCDC_VDINT2 2
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#define IRQ_DM355_IPIPE_HST 3
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#define IRQ_DM355_H3AINT 4
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#define IRQ_DM355_IPIPE_SDR 5
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#define IRQ_DM355_IPIPEIFINT 6
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#define IRQ_DM355_OSDINT 7
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#define IRQ_DM355_VENCINT 8
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#define IRQ_DM355_IMCOPINT 11
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#define IRQ_DM355_RTOINT 13
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#define IRQ_DM355_TINT4 13
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#define IRQ_DM355_TINT2_TINT12 13
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#define IRQ_DM355_UARTINT2 14
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#define IRQ_DM355_TINT5 14
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#define IRQ_DM355_TINT2_TINT34 14
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#define IRQ_DM355_TINT6 15
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#define IRQ_DM355_TINT3_TINT12 15
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#define IRQ_DM355_SPINT1_0 17
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#define IRQ_DM355_SPINT1_1 18
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#define IRQ_DM355_SPINT2_0 19
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#define IRQ_DM355_SPINT2_1 21
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#define IRQ_DM355_TINT7 22
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#define IRQ_DM355_TINT3_TINT34 22
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#define IRQ_DM355_SDIOINT0 23
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#define IRQ_DM355_MMCINT0 26
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#define IRQ_DM355_MSINT 26
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#define IRQ_DM355_MMCINT1 27
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#define IRQ_DM355_PWMINT3 28
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#define IRQ_DM355_SDIOINT1 31
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#define IRQ_DM355_SPINT0_0 42
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#define IRQ_DM355_SPINT0_1 43
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#define IRQ_DM355_GPIO0 44
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#define IRQ_DM355_GPIO1 45
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#define IRQ_DM355_GPIO2 46
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#define IRQ_DM355_GPIO3 47
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#define IRQ_DM355_GPIO4 48
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#define IRQ_DM355_GPIO5 49
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#define IRQ_DM355_GPIO6 50
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#define IRQ_DM355_GPIO7 51
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#define IRQ_DM355_GPIO8 52
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#define IRQ_DM355_GPIO9 53
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#define IRQ_DM355_GPIOBNK0 54
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#define IRQ_DM355_GPIOBNK1 55
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#define IRQ_DM355_GPIOBNK2 56
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#define IRQ_DM355_GPIOBNK3 57
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#define IRQ_DM355_GPIOBNK4 58
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#define IRQ_DM355_GPIOBNK5 59
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#define IRQ_DM355_GPIOBNK6 60
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#endif /* __ASM_ARCH_IRQS_H */
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