5154e9f126
BUSWAIT is a 4-bit-wide value that controls the number of access waits from the CPU to on-chip USB module. b'0000 inserts 0 wait (2 access cycles) and b'1111 inserts 15 waits (17 access cycles, hardware initial value), respectively. BUSWAIT value depends on peripheral clock frequency supplied to on-chip of each CPU, hence should be configurable through platform data. Note that this patch assumes that b'0000 (0 wait, 2 access cycles) is rerely used and considered as invalid. If valid 'buswait' data is not provided by platform, initial b'1111 (15 waits, 17 access cycles) will be applied as a safe default. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Felipe Balbi <balbi@ti.com> |
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| .. | ||
| association.h | ||
| atmel_usba_udc.h | ||
| audio-v2.h | ||
| audio.h | ||
| c67x00.h | ||
| cdc.h | ||
| ch9.h | ||
| ch11.h | ||
| composite.h | ||
| ehci_def.h | ||
| functionfs.h | ||
| g_hid.h | ||
| g_printer.h | ||
| gadget.h | ||
| gadgetfs.h | ||
| gpio_vbus.h | ||
| hcd.h | ||
| input.h | ||
| intel_mid_otg.h | ||
| iowarrior.h | ||
| irda.h | ||
| isp116x.h | ||
| isp1362.h | ||
| isp1760.h | ||
| Kbuild | ||
| langwell_otg.h | ||
| langwell_udc.h | ||
| m66592.h | ||
| midi.h | ||
| msm_hsusb_hw.h | ||
| msm_hsusb.h | ||
| musb.h | ||
| net2280.h | ||
| otg.h | ||
| quirks.h | ||
| r8a66597.h | ||
| renesas_usbhs.h | ||
| rndis_host.h | ||
| serial.h | ||
| sl811.h | ||
| storage.h | ||
| tmc.h | ||
| ulpi.h | ||
| usbnet.h | ||
| video.h | ||
| wusb-wa.h | ||
| wusb.h | ||