dc98e4145d
This patch moves header files from plat-s3c24xx to plat-samsung to remove plat-s3c24xx directory to make one plat-samsung directory for Samsung SoCs. And this patch includes fixing coding style, too. Cc: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
71 lines
2.2 KiB
C
71 lines
2.2 KiB
C
/* arch/arm/plat-samsung/include/plat/regs-iis.h
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*
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* Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
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* http://www.simtec.co.uk/products/SWLINUX/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* S3C2410 IIS register definition
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*/
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#ifndef __ASM_ARCH_REGS_IIS_H
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#define __ASM_ARCH_REGS_IIS_H
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#define S3C2410_IISCON (0x00)
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#define S3C2410_IISCON_LRINDEX (1 << 8)
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#define S3C2410_IISCON_TXFIFORDY (1 << 7)
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#define S3C2410_IISCON_RXFIFORDY (1 << 6)
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#define S3C2410_IISCON_TXDMAEN (1 << 5)
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#define S3C2410_IISCON_RXDMAEN (1 << 4)
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#define S3C2410_IISCON_TXIDLE (1 << 3)
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#define S3C2410_IISCON_RXIDLE (1 << 2)
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#define S3C2410_IISCON_PSCEN (1 << 1)
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#define S3C2410_IISCON_IISEN (1 << 0)
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#define S3C2410_IISMOD (0x04)
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#define S3C2440_IISMOD_MPLL (1 << 9)
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#define S3C2410_IISMOD_SLAVE (1 << 8)
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#define S3C2410_IISMOD_NOXFER (0 << 6)
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#define S3C2410_IISMOD_RXMODE (1 << 6)
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#define S3C2410_IISMOD_TXMODE (2 << 6)
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#define S3C2410_IISMOD_TXRXMODE (3 << 6)
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#define S3C2410_IISMOD_LR_LLOW (0 << 5)
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#define S3C2410_IISMOD_LR_RLOW (1 << 5)
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#define S3C2410_IISMOD_IIS (0 << 4)
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#define S3C2410_IISMOD_MSB (1 << 4)
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#define S3C2410_IISMOD_8BIT (0 << 3)
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#define S3C2410_IISMOD_16BIT (1 << 3)
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#define S3C2410_IISMOD_BITMASK (1 << 3)
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#define S3C2410_IISMOD_256FS (0 << 2)
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#define S3C2410_IISMOD_384FS (1 << 2)
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#define S3C2410_IISMOD_16FS (0 << 0)
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#define S3C2410_IISMOD_32FS (1 << 0)
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#define S3C2410_IISMOD_48FS (2 << 0)
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#define S3C2410_IISMOD_FS_MASK (3 << 0)
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#define S3C2410_IISPSR (0x08)
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#define S3C2410_IISPSR_INTMASK (31 << 5)
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#define S3C2410_IISPSR_INTSHIFT (5)
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#define S3C2410_IISPSR_EXTMASK (31 << 0)
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#define S3C2410_IISPSR_EXTSHFIT (0)
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#define S3C2410_IISFCON (0x0c)
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#define S3C2410_IISFCON_TXDMA (1 << 15)
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#define S3C2410_IISFCON_RXDMA (1 << 14)
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#define S3C2410_IISFCON_TXENABLE (1 << 13)
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#define S3C2410_IISFCON_RXENABLE (1 << 12)
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#define S3C2410_IISFCON_TXMASK (0x3f << 6)
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#define S3C2410_IISFCON_TXSHIFT (6)
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#define S3C2410_IISFCON_RXMASK (0x3f)
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#define S3C2410_IISFCON_RXSHIFT (0)
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#define S3C2410_IISFIFO (0x10)
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#endif /* __ASM_ARCH_REGS_IIS_H */
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