991312d88c
The AR9003 TX/RX gain is currently initialized with the other components, so for now AR9003 does not implment this callback, after hardware bring up we can test moving the TX/RX gain there as well and if it works well move them to its own callback as well. Since all INI stuff is now moved out hw.c no longer needs to include and touch any original INI headers/structs. Signed-off-by: Luis R. Rodriguez <lrodriguez@atheros.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
505 lines
17 KiB
C
505 lines
17 KiB
C
/*
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* Copyright (c) 2008-2010 Atheros Communications Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#include "hw.h"
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#include "ar5008_initvals.h"
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#include "ar9001_initvals.h"
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#include "ar9002_initvals.h"
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/* General hardware code for the A5008/AR9001/AR9002 hadware families */
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static bool ar9002_hw_macversion_supported(u32 macversion)
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{
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switch (macversion) {
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case AR_SREV_VERSION_5416_PCI:
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case AR_SREV_VERSION_5416_PCIE:
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case AR_SREV_VERSION_9160:
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case AR_SREV_VERSION_9100:
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case AR_SREV_VERSION_9280:
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case AR_SREV_VERSION_9285:
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case AR_SREV_VERSION_9287:
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case AR_SREV_VERSION_9271:
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return true;
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default:
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break;
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}
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return false;
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}
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static void ar9002_hw_init_mode_regs(struct ath_hw *ah)
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{
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if (AR_SREV_9271(ah)) {
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INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271,
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ARRAY_SIZE(ar9271Modes_9271), 6);
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INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271,
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ARRAY_SIZE(ar9271Common_9271), 2);
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INIT_INI_ARRAY(&ah->iniCommon_normal_cck_fir_coeff_9271,
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ar9271Common_normal_cck_fir_coeff_9271,
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ARRAY_SIZE(ar9271Common_normal_cck_fir_coeff_9271), 2);
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INIT_INI_ARRAY(&ah->iniCommon_japan_2484_cck_fir_coeff_9271,
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ar9271Common_japan_2484_cck_fir_coeff_9271,
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ARRAY_SIZE(ar9271Common_japan_2484_cck_fir_coeff_9271), 2);
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INIT_INI_ARRAY(&ah->iniModes_9271_1_0_only,
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ar9271Modes_9271_1_0_only,
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ARRAY_SIZE(ar9271Modes_9271_1_0_only), 6);
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INIT_INI_ARRAY(&ah->iniModes_9271_ANI_reg, ar9271Modes_9271_ANI_reg,
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ARRAY_SIZE(ar9271Modes_9271_ANI_reg), 6);
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INIT_INI_ARRAY(&ah->iniModes_high_power_tx_gain_9271,
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ar9271Modes_high_power_tx_gain_9271,
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ARRAY_SIZE(ar9271Modes_high_power_tx_gain_9271), 6);
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INIT_INI_ARRAY(&ah->iniModes_normal_power_tx_gain_9271,
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ar9271Modes_normal_power_tx_gain_9271,
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ARRAY_SIZE(ar9271Modes_normal_power_tx_gain_9271), 6);
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return;
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}
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if (AR_SREV_9287_11_OR_LATER(ah)) {
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INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1,
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ARRAY_SIZE(ar9287Modes_9287_1_1), 6);
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INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1,
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ARRAY_SIZE(ar9287Common_9287_1_1), 2);
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if (ah->config.pcie_clock_req)
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INIT_INI_ARRAY(&ah->iniPcieSerdes,
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ar9287PciePhy_clkreq_off_L1_9287_1_1,
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ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_1), 2);
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else
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INIT_INI_ARRAY(&ah->iniPcieSerdes,
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ar9287PciePhy_clkreq_always_on_L1_9287_1_1,
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ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_1),
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2);
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} else if (AR_SREV_9287_10_OR_LATER(ah)) {
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INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_0,
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ARRAY_SIZE(ar9287Modes_9287_1_0), 6);
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INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_0,
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ARRAY_SIZE(ar9287Common_9287_1_0), 2);
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if (ah->config.pcie_clock_req)
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INIT_INI_ARRAY(&ah->iniPcieSerdes,
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ar9287PciePhy_clkreq_off_L1_9287_1_0,
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ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_0), 2);
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else
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INIT_INI_ARRAY(&ah->iniPcieSerdes,
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ar9287PciePhy_clkreq_always_on_L1_9287_1_0,
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ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_0),
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2);
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} else if (AR_SREV_9285_12_OR_LATER(ah)) {
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INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2,
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ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
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INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2,
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ARRAY_SIZE(ar9285Common_9285_1_2), 2);
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if (ah->config.pcie_clock_req) {
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INIT_INI_ARRAY(&ah->iniPcieSerdes,
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ar9285PciePhy_clkreq_off_L1_9285_1_2,
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ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
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} else {
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INIT_INI_ARRAY(&ah->iniPcieSerdes,
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ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
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ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
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2);
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}
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} else if (AR_SREV_9285_10_OR_LATER(ah)) {
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INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285,
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ARRAY_SIZE(ar9285Modes_9285), 6);
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INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285,
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ARRAY_SIZE(ar9285Common_9285), 2);
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if (ah->config.pcie_clock_req) {
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INIT_INI_ARRAY(&ah->iniPcieSerdes,
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ar9285PciePhy_clkreq_off_L1_9285,
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ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
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} else {
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INIT_INI_ARRAY(&ah->iniPcieSerdes,
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ar9285PciePhy_clkreq_always_on_L1_9285,
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ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
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}
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} else if (AR_SREV_9280_20_OR_LATER(ah)) {
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INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2,
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ARRAY_SIZE(ar9280Modes_9280_2), 6);
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INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2,
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ARRAY_SIZE(ar9280Common_9280_2), 2);
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if (ah->config.pcie_clock_req) {
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INIT_INI_ARRAY(&ah->iniPcieSerdes,
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ar9280PciePhy_clkreq_off_L1_9280,
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ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280), 2);
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} else {
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INIT_INI_ARRAY(&ah->iniPcieSerdes,
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ar9280PciePhy_clkreq_always_on_L1_9280,
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ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
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}
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INIT_INI_ARRAY(&ah->iniModesAdditional,
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ar9280Modes_fast_clock_9280_2,
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ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
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} else if (AR_SREV_9280_10_OR_LATER(ah)) {
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INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280,
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ARRAY_SIZE(ar9280Modes_9280), 6);
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INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280,
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ARRAY_SIZE(ar9280Common_9280), 2);
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} else if (AR_SREV_9160_10_OR_LATER(ah)) {
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INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160,
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ARRAY_SIZE(ar5416Modes_9160), 6);
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INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160,
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ARRAY_SIZE(ar5416Common_9160), 2);
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INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160,
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ARRAY_SIZE(ar5416Bank0_9160), 2);
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INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160,
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ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
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INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160,
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ARRAY_SIZE(ar5416Bank1_9160), 2);
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INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160,
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ARRAY_SIZE(ar5416Bank2_9160), 2);
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INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160,
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ARRAY_SIZE(ar5416Bank3_9160), 3);
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INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160,
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ARRAY_SIZE(ar5416Bank6_9160), 3);
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INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160,
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ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
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INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160,
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ARRAY_SIZE(ar5416Bank7_9160), 2);
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if (AR_SREV_9160_11(ah)) {
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INIT_INI_ARRAY(&ah->iniAddac,
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ar5416Addac_91601_1,
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ARRAY_SIZE(ar5416Addac_91601_1), 2);
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} else {
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INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160,
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ARRAY_SIZE(ar5416Addac_9160), 2);
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}
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} else if (AR_SREV_9100_OR_LATER(ah)) {
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INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100,
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ARRAY_SIZE(ar5416Modes_9100), 6);
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INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100,
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ARRAY_SIZE(ar5416Common_9100), 2);
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INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100,
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ARRAY_SIZE(ar5416Bank0_9100), 2);
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INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100,
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ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
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INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100,
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ARRAY_SIZE(ar5416Bank1_9100), 2);
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INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100,
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ARRAY_SIZE(ar5416Bank2_9100), 2);
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INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100,
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ARRAY_SIZE(ar5416Bank3_9100), 3);
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INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100,
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ARRAY_SIZE(ar5416Bank6_9100), 3);
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INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100,
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ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
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INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100,
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ARRAY_SIZE(ar5416Bank7_9100), 2);
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INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100,
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ARRAY_SIZE(ar5416Addac_9100), 2);
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} else {
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INIT_INI_ARRAY(&ah->iniModes, ar5416Modes,
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ARRAY_SIZE(ar5416Modes), 6);
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INIT_INI_ARRAY(&ah->iniCommon, ar5416Common,
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ARRAY_SIZE(ar5416Common), 2);
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INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0,
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ARRAY_SIZE(ar5416Bank0), 2);
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INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain,
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ARRAY_SIZE(ar5416BB_RfGain), 3);
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INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1,
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ARRAY_SIZE(ar5416Bank1), 2);
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INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2,
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ARRAY_SIZE(ar5416Bank2), 2);
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INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3,
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ARRAY_SIZE(ar5416Bank3), 3);
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INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6,
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ARRAY_SIZE(ar5416Bank6), 3);
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INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC,
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ARRAY_SIZE(ar5416Bank6TPC), 3);
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INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7,
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ARRAY_SIZE(ar5416Bank7), 2);
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INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac,
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ARRAY_SIZE(ar5416Addac), 2);
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}
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}
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/* Support for Japan ch.14 (2484) spread */
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void ar9002_hw_cck_chan14_spread(struct ath_hw *ah)
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{
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if (AR_SREV_9287_11_OR_LATER(ah)) {
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INIT_INI_ARRAY(&ah->iniCckfirNormal,
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ar9287Common_normal_cck_fir_coeff_92871_1,
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ARRAY_SIZE(ar9287Common_normal_cck_fir_coeff_92871_1),
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2);
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INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
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ar9287Common_japan_2484_cck_fir_coeff_92871_1,
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ARRAY_SIZE(ar9287Common_japan_2484_cck_fir_coeff_92871_1),
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2);
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}
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}
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static void ar9280_20_hw_init_rxgain_ini(struct ath_hw *ah)
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{
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u32 rxgain_type;
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if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >=
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AR5416_EEP_MINOR_VER_17) {
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rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE);
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if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
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INIT_INI_ARRAY(&ah->iniModesRxGain,
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ar9280Modes_backoff_13db_rxgain_9280_2,
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ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
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else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
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INIT_INI_ARRAY(&ah->iniModesRxGain,
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ar9280Modes_backoff_23db_rxgain_9280_2,
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ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
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else
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INIT_INI_ARRAY(&ah->iniModesRxGain,
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ar9280Modes_original_rxgain_9280_2,
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ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
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} else {
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INIT_INI_ARRAY(&ah->iniModesRxGain,
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ar9280Modes_original_rxgain_9280_2,
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ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
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}
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}
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static void ar9280_20_hw_init_txgain_ini(struct ath_hw *ah)
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{
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u32 txgain_type;
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if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >=
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AR5416_EEP_MINOR_VER_19) {
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txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
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if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
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INIT_INI_ARRAY(&ah->iniModesTxGain,
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ar9280Modes_high_power_tx_gain_9280_2,
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ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
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else
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INIT_INI_ARRAY(&ah->iniModesTxGain,
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ar9280Modes_original_tx_gain_9280_2,
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ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
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} else {
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INIT_INI_ARRAY(&ah->iniModesTxGain,
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ar9280Modes_original_tx_gain_9280_2,
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ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
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}
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}
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static void ar9002_hw_init_mode_gain_regs(struct ath_hw *ah)
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{
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if (AR_SREV_9287_11_OR_LATER(ah))
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INIT_INI_ARRAY(&ah->iniModesRxGain,
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ar9287Modes_rx_gain_9287_1_1,
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ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_1), 6);
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else if (AR_SREV_9287_10(ah))
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INIT_INI_ARRAY(&ah->iniModesRxGain,
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ar9287Modes_rx_gain_9287_1_0,
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ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_0), 6);
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else if (AR_SREV_9280_20(ah))
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ar9280_20_hw_init_rxgain_ini(ah);
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if (AR_SREV_9287_11_OR_LATER(ah)) {
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INIT_INI_ARRAY(&ah->iniModesTxGain,
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ar9287Modes_tx_gain_9287_1_1,
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ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_1), 6);
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} else if (AR_SREV_9287_10(ah)) {
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INIT_INI_ARRAY(&ah->iniModesTxGain,
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ar9287Modes_tx_gain_9287_1_0,
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ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_0), 6);
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} else if (AR_SREV_9280_20(ah)) {
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ar9280_20_hw_init_txgain_ini(ah);
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} else if (AR_SREV_9285_12_OR_LATER(ah)) {
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u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
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/* txgain table */
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if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) {
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if (AR_SREV_9285E_20(ah)) {
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INIT_INI_ARRAY(&ah->iniModesTxGain,
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ar9285Modes_XE2_0_high_power,
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ARRAY_SIZE(
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ar9285Modes_XE2_0_high_power), 6);
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} else {
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INIT_INI_ARRAY(&ah->iniModesTxGain,
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ar9285Modes_high_power_tx_gain_9285_1_2,
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ARRAY_SIZE(
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ar9285Modes_high_power_tx_gain_9285_1_2), 6);
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}
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} else {
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if (AR_SREV_9285E_20(ah)) {
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INIT_INI_ARRAY(&ah->iniModesTxGain,
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ar9285Modes_XE2_0_normal_power,
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ARRAY_SIZE(
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ar9285Modes_XE2_0_normal_power), 6);
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} else {
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INIT_INI_ARRAY(&ah->iniModesTxGain,
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ar9285Modes_original_tx_gain_9285_1_2,
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ARRAY_SIZE(
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ar9285Modes_original_tx_gain_9285_1_2), 6);
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}
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}
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}
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}
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/*
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* Helper for ASPM support.
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*
|
|
* Disable PLL when in L0s as well as receiver clock when in L1.
|
|
* This power saving option must be enabled through the SerDes.
|
|
*
|
|
* Programming the SerDes must go through the same 288 bit serial shift
|
|
* register as the other analog registers. Hence the 9 writes.
|
|
*/
|
|
static void ar9002_hw_configpcipowersave(struct ath_hw *ah,
|
|
int restore,
|
|
int power_off)
|
|
{
|
|
u8 i;
|
|
u32 val;
|
|
|
|
if (ah->is_pciexpress != true)
|
|
return;
|
|
|
|
/* Do not touch SerDes registers */
|
|
if (ah->config.pcie_powersave_enable == 2)
|
|
return;
|
|
|
|
/* Nothing to do on restore for 11N */
|
|
if (!restore) {
|
|
if (AR_SREV_9280_20_OR_LATER(ah)) {
|
|
/*
|
|
* AR9280 2.0 or later chips use SerDes values from the
|
|
* initvals.h initialized depending on chipset during
|
|
* __ath9k_hw_init()
|
|
*/
|
|
for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
|
|
REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
|
|
INI_RA(&ah->iniPcieSerdes, i, 1));
|
|
}
|
|
} else if (AR_SREV_9280(ah) &&
|
|
(ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) {
|
|
REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
|
|
REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
|
|
|
|
/* RX shut off when elecidle is asserted */
|
|
REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
|
|
REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
|
|
REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
|
|
|
|
/* Shut off CLKREQ active in L1 */
|
|
if (ah->config.pcie_clock_req)
|
|
REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
|
|
else
|
|
REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
|
|
|
|
REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
|
|
REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
|
|
REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
|
|
|
|
/* Load the new settings */
|
|
REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
|
|
|
|
} else {
|
|
REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
|
|
REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
|
|
|
|
/* RX shut off when elecidle is asserted */
|
|
REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
|
|
REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
|
|
REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
|
|
|
|
/*
|
|
* Ignore ah->ah_config.pcie_clock_req setting for
|
|
* pre-AR9280 11n
|
|
*/
|
|
REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
|
|
|
|
REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
|
|
REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
|
|
REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
|
|
|
|
/* Load the new settings */
|
|
REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
|
|
}
|
|
|
|
udelay(1000);
|
|
|
|
/* set bit 19 to allow forcing of pcie core into L1 state */
|
|
REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
|
|
|
|
/* Several PCIe massages to ensure proper behaviour */
|
|
if (ah->config.pcie_waen) {
|
|
val = ah->config.pcie_waen;
|
|
if (!power_off)
|
|
val &= (~AR_WA_D3_L1_DISABLE);
|
|
} else {
|
|
if (AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
|
|
AR_SREV_9287(ah)) {
|
|
val = AR9285_WA_DEFAULT;
|
|
if (!power_off)
|
|
val &= (~AR_WA_D3_L1_DISABLE);
|
|
} else if (AR_SREV_9280(ah)) {
|
|
/*
|
|
* On AR9280 chips bit 22 of 0x4004 needs to be
|
|
* set otherwise card may disappear.
|
|
*/
|
|
val = AR9280_WA_DEFAULT;
|
|
if (!power_off)
|
|
val &= (~AR_WA_D3_L1_DISABLE);
|
|
} else
|
|
val = AR_WA_DEFAULT;
|
|
}
|
|
|
|
REG_WRITE(ah, AR_WA, val);
|
|
}
|
|
|
|
if (power_off) {
|
|
/*
|
|
* Set PCIe workaround bits
|
|
* bit 14 in WA register (disable L1) should only
|
|
* be set when device enters D3 and be cleared
|
|
* when device comes back to D0.
|
|
*/
|
|
if (ah->config.pcie_waen) {
|
|
if (ah->config.pcie_waen & AR_WA_D3_L1_DISABLE)
|
|
REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
|
|
} else {
|
|
if (((AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
|
|
AR_SREV_9287(ah)) &&
|
|
(AR9285_WA_DEFAULT & AR_WA_D3_L1_DISABLE)) ||
|
|
(AR_SREV_9280(ah) &&
|
|
(AR9280_WA_DEFAULT & AR_WA_D3_L1_DISABLE))) {
|
|
REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Sets up the AR5008/AR9001/AR9002 hardware familiy callbacks */
|
|
void ar9002_hw_attach_ops(struct ath_hw *ah)
|
|
{
|
|
struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
|
|
struct ath_hw_ops *ops = ath9k_hw_ops(ah);
|
|
|
|
priv_ops->init_mode_regs = ar9002_hw_init_mode_regs;
|
|
priv_ops->init_mode_gain_regs = ar9002_hw_init_mode_gain_regs;
|
|
priv_ops->macversion_supported = ar9002_hw_macversion_supported;
|
|
|
|
ops->config_pci_powersave = ar9002_hw_configpcipowersave;
|
|
|
|
ar5008_hw_attach_phy_ops(ah);
|
|
if (AR_SREV_9280_10_OR_LATER(ah))
|
|
ar9002_hw_attach_phy_ops(ah);
|
|
|
|
ar9002_hw_attach_calib_ops(ah);
|
|
ar9002_hw_attach_mac_ops(ah);
|
|
}
|