588ef76935
Enable svc access to cp6 via an undefined instruction hook. Do not enable access for usr code. This patch also makes iop13xx select PLAT_IOP, this requires a small change to drivers/i2c/busses/i2c-iop3xx.c. Per Lennert Buytenhek's note, the cp6 trap routine is moved to arch/arm/plat-iop Per Nicolas Pitre's note, the cp_wait is skipped since the latency to return to the faulting function is longer than cp_wait. Signed-off-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
130 lines
2.6 KiB
C
130 lines
2.6 KiB
C
/*
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* arch/arm/mach-iop33x/irq.c
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*
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* Generic IOP331 IRQ handling functionality
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*
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* Author: Dave Jiang <dave.jiang@intel.com>
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* Copyright (C) 2003 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/list.h>
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#include <asm/mach/irq.h>
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#include <asm/irq.h>
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#include <asm/hardware.h>
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#include <asm/mach-types.h>
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static u32 iop33x_mask0;
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static u32 iop33x_mask1;
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static inline void intctl0_write(u32 val)
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{
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iop3xx_cp6_enable();
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asm volatile("mcr p6, 0, %0, c0, c0, 0" : : "r" (val));
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iop3xx_cp6_disable();
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}
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static inline void intctl1_write(u32 val)
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{
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iop3xx_cp6_enable();
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asm volatile("mcr p6, 0, %0, c1, c0, 0" : : "r" (val));
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iop3xx_cp6_disable();
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}
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static inline void intstr0_write(u32 val)
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{
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iop3xx_cp6_enable();
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asm volatile("mcr p6, 0, %0, c2, c0, 0" : : "r" (val));
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iop3xx_cp6_disable();
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}
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static inline void intstr1_write(u32 val)
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{
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iop3xx_cp6_enable();
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asm volatile("mcr p6, 0, %0, c3, c0, 0" : : "r" (val));
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iop3xx_cp6_disable();
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}
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static inline void intbase_write(u32 val)
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{
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iop3xx_cp6_enable();
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asm volatile("mcr p6, 0, %0, c12, c0, 0" : : "r" (val));
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iop3xx_cp6_disable();
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}
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static inline void intsize_write(u32 val)
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{
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iop3xx_cp6_enable();
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asm volatile("mcr p6, 0, %0, c13, c0, 0" : : "r" (val));
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iop3xx_cp6_disable();
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}
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static void
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iop33x_irq_mask1 (unsigned int irq)
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{
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iop33x_mask0 &= ~(1 << irq);
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intctl0_write(iop33x_mask0);
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}
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static void
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iop33x_irq_mask2 (unsigned int irq)
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{
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iop33x_mask1 &= ~(1 << (irq - 32));
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intctl1_write(iop33x_mask1);
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}
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static void
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iop33x_irq_unmask1(unsigned int irq)
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{
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iop33x_mask0 |= 1 << irq;
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intctl0_write(iop33x_mask0);
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}
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static void
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iop33x_irq_unmask2(unsigned int irq)
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{
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iop33x_mask1 |= (1 << (irq - 32));
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intctl1_write(iop33x_mask1);
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}
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struct irq_chip iop33x_irqchip1 = {
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.name = "IOP33x-1",
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.ack = iop33x_irq_mask1,
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.mask = iop33x_irq_mask1,
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.unmask = iop33x_irq_unmask1,
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};
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struct irq_chip iop33x_irqchip2 = {
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.name = "IOP33x-2",
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.ack = iop33x_irq_mask2,
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.mask = iop33x_irq_mask2,
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.unmask = iop33x_irq_unmask2,
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};
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void __init iop33x_init_irq(void)
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{
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int i;
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iop_init_cp6_handler();
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intctl0_write(0);
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intctl1_write(0);
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intstr0_write(0);
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intstr1_write(0);
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intbase_write(0);
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intsize_write(1);
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if (machine_is_iq80331())
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*IOP3XX_PCIIRSR = 0x0f;
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for (i = 0; i < NR_IRQS; i++) {
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set_irq_chip(i, (i < 32) ? &iop33x_irqchip1 : &iop33x_irqchip2);
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set_irq_handler(i, handle_level_irq);
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set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
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}
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}
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