ad756a1603
This patch handles PCID/INVPCID for guests. Process-context identifiers (PCIDs) are a facility by which a logical processor may cache information for multiple linear-address spaces so that the processor may retain cached information when software switches to a different linear address space. Refer to section 4.10.1 in IA32 Intel Software Developer's Manual Volume 3A for details. For guests with EPT, the PCID feature is enabled and INVPCID behaves as running natively. For guests without EPT, the PCID feature is disabled and INVPCID triggers #UD. Signed-off-by: Junjie Mao <junjie.mao@intel.com> Signed-off-by: Avi Kivity <avi@redhat.com>
106 lines
3.7 KiB
C
106 lines
3.7 KiB
C
#ifndef _ASM_X86_PROCESSOR_FLAGS_H
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#define _ASM_X86_PROCESSOR_FLAGS_H
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/* Various flags defined: can be included from assembler. */
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/*
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* EFLAGS bits
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*/
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#define X86_EFLAGS_CF 0x00000001 /* Carry Flag */
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#define X86_EFLAGS_BIT1 0x00000002 /* Bit 1 - always on */
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#define X86_EFLAGS_PF 0x00000004 /* Parity Flag */
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#define X86_EFLAGS_AF 0x00000010 /* Auxiliary carry Flag */
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#define X86_EFLAGS_ZF 0x00000040 /* Zero Flag */
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#define X86_EFLAGS_SF 0x00000080 /* Sign Flag */
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#define X86_EFLAGS_TF 0x00000100 /* Trap Flag */
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#define X86_EFLAGS_IF 0x00000200 /* Interrupt Flag */
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#define X86_EFLAGS_DF 0x00000400 /* Direction Flag */
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#define X86_EFLAGS_OF 0x00000800 /* Overflow Flag */
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#define X86_EFLAGS_IOPL 0x00003000 /* IOPL mask */
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#define X86_EFLAGS_NT 0x00004000 /* Nested Task */
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#define X86_EFLAGS_RF 0x00010000 /* Resume Flag */
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#define X86_EFLAGS_VM 0x00020000 /* Virtual Mode */
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#define X86_EFLAGS_AC 0x00040000 /* Alignment Check */
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#define X86_EFLAGS_VIF 0x00080000 /* Virtual Interrupt Flag */
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#define X86_EFLAGS_VIP 0x00100000 /* Virtual Interrupt Pending */
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#define X86_EFLAGS_ID 0x00200000 /* CPUID detection flag */
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/*
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* Basic CPU control in CR0
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*/
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#define X86_CR0_PE 0x00000001 /* Protection Enable */
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#define X86_CR0_MP 0x00000002 /* Monitor Coprocessor */
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#define X86_CR0_EM 0x00000004 /* Emulation */
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#define X86_CR0_TS 0x00000008 /* Task Switched */
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#define X86_CR0_ET 0x00000010 /* Extension Type */
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#define X86_CR0_NE 0x00000020 /* Numeric Error */
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#define X86_CR0_WP 0x00010000 /* Write Protect */
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#define X86_CR0_AM 0x00040000 /* Alignment Mask */
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#define X86_CR0_NW 0x20000000 /* Not Write-through */
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#define X86_CR0_CD 0x40000000 /* Cache Disable */
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#define X86_CR0_PG 0x80000000 /* Paging */
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/*
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* Paging options in CR3
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*/
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#define X86_CR3_PWT 0x00000008 /* Page Write Through */
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#define X86_CR3_PCD 0x00000010 /* Page Cache Disable */
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#define X86_CR3_PCID_MASK 0x00000fff /* PCID Mask */
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/*
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* Intel CPU features in CR4
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*/
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#define X86_CR4_VME 0x00000001 /* enable vm86 extensions */
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#define X86_CR4_PVI 0x00000002 /* virtual interrupts flag enable */
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#define X86_CR4_TSD 0x00000004 /* disable time stamp at ipl 3 */
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#define X86_CR4_DE 0x00000008 /* enable debugging extensions */
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#define X86_CR4_PSE 0x00000010 /* enable page size extensions */
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#define X86_CR4_PAE 0x00000020 /* enable physical address extensions */
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#define X86_CR4_MCE 0x00000040 /* Machine check enable */
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#define X86_CR4_PGE 0x00000080 /* enable global pages */
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#define X86_CR4_PCE 0x00000100 /* enable performance counters at ipl 3 */
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#define X86_CR4_OSFXSR 0x00000200 /* enable fast FPU save and restore */
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#define X86_CR4_OSXMMEXCPT 0x00000400 /* enable unmasked SSE exceptions */
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#define X86_CR4_VMXE 0x00002000 /* enable VMX virtualization */
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#define X86_CR4_RDWRGSFS 0x00010000 /* enable RDWRGSFS support */
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#define X86_CR4_PCIDE 0x00020000 /* enable PCID support */
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#define X86_CR4_OSXSAVE 0x00040000 /* enable xsave and xrestore */
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#define X86_CR4_SMEP 0x00100000 /* enable SMEP support */
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/*
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* x86-64 Task Priority Register, CR8
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*/
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#define X86_CR8_TPR 0x0000000F /* task priority register */
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/*
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* AMD and Transmeta use MSRs for configuration; see <asm/msr-index.h>
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*/
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/*
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* NSC/Cyrix CPU configuration register indexes
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*/
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#define CX86_PCR0 0x20
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#define CX86_GCR 0xb8
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#define CX86_CCR0 0xc0
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#define CX86_CCR1 0xc1
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#define CX86_CCR2 0xc2
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#define CX86_CCR3 0xc3
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#define CX86_CCR4 0xe8
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#define CX86_CCR5 0xe9
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#define CX86_CCR6 0xea
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#define CX86_CCR7 0xeb
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#define CX86_PCR1 0xf0
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#define CX86_DIR0 0xfe
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#define CX86_DIR1 0xff
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#define CX86_ARR_BASE 0xc4
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#define CX86_RCR_BASE 0xdc
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#ifdef __KERNEL__
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#ifdef CONFIG_VM86
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#define X86_VM_MASK X86_EFLAGS_VM
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#else
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#define X86_VM_MASK 0 /* No VM86 support */
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#endif
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#endif
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#endif /* _ASM_X86_PROCESSOR_FLAGS_H */
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