1c83af5f9d
The more modern ColdFire parts (even if based on older version cores) have separate user and supervisor stack pointers (a7 register). Modify the ColdFire CPU setup and exception code to enable and use this on parts that have it. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
153 lines
4.5 KiB
C
153 lines
4.5 KiB
C
/****************************************************************************/
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/*
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* mcfcache.h -- ColdFire CPU cache support code
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*
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* (C) Copyright 2004, Greg Ungerer <gerg@snapgear.com>
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*/
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/****************************************************************************/
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#ifndef __M68KNOMMU_MCFCACHE_H
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#define __M68KNOMMU_MCFCACHE_H
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/****************************************************************************/
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/*
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* The different ColdFire families have different cache arrangments.
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* Everything from a small instruction only cache, to configurable
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* data and/or instruction cache, to unified instruction/data, to
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* harvard style separate instruction and data caches.
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*/
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#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || defined(CONFIG_M5272)
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/*
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* Simple version 2 core cache. These have instruction cache only,
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* we just need to invalidate it and enable it.
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*/
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.macro CACHE_ENABLE
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movel #0x01000000,%d0 /* invalidate cache cmd */
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movec %d0,%CACR /* do invalidate cache */
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movel #0x80000100,%d0 /* setup cache mask */
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movec %d0,%CACR /* enable cache */
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.endm
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#endif /* CONFIG_M5206 || CONFIG_M5206e || CONFIG_M5272 */
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#if defined(CONFIG_M523x) || defined(CONFIG_M527x)
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/*
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* New version 2 cores have a configurable split cache arrangement.
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* For now I am just enabling instruction cache - but ultimately I
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* think a split instruction/data cache would be better.
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*/
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.macro CACHE_ENABLE
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movel #0x01400000,%d0
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movec %d0,%CACR /* invalidate cache */
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nop
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movel #0x0000c000,%d0 /* set SDRAM cached only */
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movec %d0,%ACR0
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movel #0x00000000,%d0 /* no other regions cached */
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movec %d0,%ACR1
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movel #0x80400110,%d0 /* configure cache */
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movec %d0,%CACR /* enable cache */
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nop
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.endm
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#endif /* CONFIG_M523x || CONFIG_M527x */
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#if defined(CONFIG_M528x)
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.macro CACHE_ENABLE
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nop
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movel #0x01000000, %d0
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movec %d0, %CACR /* Invalidate cache */
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nop
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movel #0x0000c020, %d0 /* Set SDRAM cached only */
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movec %d0, %ACR0
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movel #0x00000000, %d0 /* No other regions cached */
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movec %d0, %ACR1
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movel #0x80000200, %d0 /* Setup cache mask */
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movec %d0, %CACR /* Enable cache */
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nop
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.endm
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#endif /* CONFIG_M528x */
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#if defined(CONFIG_M5249) || defined(CONFIG_M5307)
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/*
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* The version 3 core cache. Oddly enough the version 2 core 5249
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* has the same SDRAM and cache setup as the version 3 cores.
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* This is a single unified instruction/data cache.
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*/
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.macro CACHE_ENABLE
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movel #0x01000000,%d0 /* invalidate whole cache */
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movec %d0,%CACR
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nop
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#if defined(DEBUGGER_COMPATIBLE_CACHE) || defined(CONFIG_SECUREEDGEMP3)
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movel #0x0000c000,%d0 /* set SDRAM cached (write-thru) */
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#else
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movel #0x0000c020,%d0 /* set SDRAM cached (copyback) */
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#endif
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movec %d0,%ACR0
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movel #0x00000000,%d0 /* no other regions cached */
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movec %d0,%ACR1
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movel #0xa0000200,%d0 /* enable cache */
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movec %d0,%CACR
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nop
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.endm
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#endif /* CONFIG_M5249 || CONFIG_M5307 */
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#if defined(CONFIG_M532x)
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.macro CACHE_ENABLE
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movel #0x01000000,%d0 /* invalidate cache cmd */
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movec %d0,%CACR /* do invalidate cache */
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nop
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movel #0x4001C000,%d0 /* set SDRAM cached (write-thru) */
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movec %d0,%ACR0
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movel #0x00000000,%d0 /* no other regions cached */
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movec %d0,%ACR1
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movel #0x80000210,%d0 /* setup cache mask */
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movec %d0,%CACR /* enable cache */
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nop
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.endm
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#endif /* CONFIG_M532x */
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#if defined(CONFIG_M5407) || defined(CONFIG_M54xx)
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#include <asm/m54xxacr.h>
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.macro CACHE_ENABLE
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/* invalidate whole cache */
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movel #(CACR_DCINVA+CACR_BCINVA+CACR_ICINVA),%d0
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movec %d0,%CACR
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nop
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/* addresses range for data cache : 0x00000000-0x0fffffff */
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movel #(0x000f0000+DATA_CACHE_MODE),%d0 /* set SDRAM cached */
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movec %d0, %ACR0
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movel #0x00000000,%d0 /* no other regions cached */
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movec %d0, %ACR1
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/* addresses range for instruction cache : 0x00000000-0x0fffffff */
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movel #(0x000f0000+INSN_CACHE_MODE),%d0 /* set SDRAM cached */
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movec %d0, %ACR2
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movel #0x00000000,%d0 /* no other regions cached */
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movec %d0, %ACR3
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/* enable caches */
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movel #(CACHE_MODE),%d0
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movec %d0,%CACR
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nop
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.endm
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#endif /* CONFIG_M5407 || CONFIG_M54xx */
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#if defined(CONFIG_M520x)
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.macro CACHE_ENABLE
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move.l #0x01000000,%d0 /* invalidate whole cache */
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movec %d0,%CACR
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nop
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move.l #0x0000c000,%d0 /* set SDRAM cached (write-thru) */
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movec %d0,%ACR0
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move.l #0x00000000,%d0 /* no other regions cached */
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movec %d0,%ACR1
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move.l #0x80400010,%d0 /* enable 8K instruction cache */
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movec %d0,%CACR
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nop
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.endm
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#endif /* CONFIG_M520x */
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/****************************************************************************/
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#endif /* __M68KNOMMU_MCFCACHE_H */
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