06109f47f2
WM8804 can run with PLL frequencies of 256xfs and 128xfs for most sample rates. At 192kHz only 128xfs is supported. The existing driver selects 128xfs automatically for some lower samples rates. By using an additional mclk_div divider, it is now possible to control the behaviour. This allows using 256xfs PLL frequency on all sample rates up to 96kHz. It should allow lower jitter and better signal quality. The behavior has to be controlled by the sound card driver, because some sample frequency share the same setting. e.g. 192kHz and 96kHz use 24.576MHz master clock. The only difference is the MCLK divider. Signed-off-by: Daniel Matuschek <daniel@matuschek.net> Tested-by: Florian Meier <florian.meier@koalo.de> Signed-off-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com> Signed-off-by: Mark Brown <broonie@linaro.org>
66 lines
1.6 KiB
C
66 lines
1.6 KiB
C
/*
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* wm8804.h -- WM8804 S/PDIF transceiver driver
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*
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* Copyright 2010 Wolfson Microelectronics plc
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*
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* Author: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef _WM8804_H
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#define _WM8804_H
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/*
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* Register values.
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*/
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#define WM8804_RST_DEVID1 0x00
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#define WM8804_DEVID2 0x01
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#define WM8804_DEVREV 0x02
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#define WM8804_PLL1 0x03
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#define WM8804_PLL2 0x04
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#define WM8804_PLL3 0x05
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#define WM8804_PLL4 0x06
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#define WM8804_PLL5 0x07
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#define WM8804_PLL6 0x08
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#define WM8804_SPDMODE 0x09
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#define WM8804_INTMASK 0x0A
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#define WM8804_INTSTAT 0x0B
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#define WM8804_SPDSTAT 0x0C
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#define WM8804_RXCHAN1 0x0D
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#define WM8804_RXCHAN2 0x0E
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#define WM8804_RXCHAN3 0x0F
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#define WM8804_RXCHAN4 0x10
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#define WM8804_RXCHAN5 0x11
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#define WM8804_SPDTX1 0x12
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#define WM8804_SPDTX2 0x13
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#define WM8804_SPDTX3 0x14
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#define WM8804_SPDTX4 0x15
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#define WM8804_SPDTX5 0x16
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#define WM8804_GPO0 0x17
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#define WM8804_GPO1 0x18
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#define WM8804_GPO2 0x1A
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#define WM8804_AIFTX 0x1B
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#define WM8804_AIFRX 0x1C
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#define WM8804_SPDRX1 0x1D
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#define WM8804_PWRDN 0x1E
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#define WM8804_REGISTER_COUNT 30
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#define WM8804_MAX_REGISTER 0x1E
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#define WM8804_TX_CLKSRC_MCLK 1
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#define WM8804_TX_CLKSRC_PLL 2
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#define WM8804_CLKOUT_SRC_CLK1 3
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#define WM8804_CLKOUT_SRC_OSCCLK 4
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#define WM8804_CLKOUT_DIV 1
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#define WM8804_MCLK_DIV 2
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#define WM8804_MCLKDIV_256FS 0
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#define WM8804_MCLKDIV_128FS 1
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#endif /* _WM8804_H */
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