8d813941b1
This gets the FEC ethernet driver working again on the lite5200 platform. The FEC driver is also compatible with the MPC5200, not only with the MPC5200B, so this adds a suitable entry to the driver's match list. Furthermore this adds the settings for the PHY in the dts file for the Lite5200. Note, that this is not exactly the same as in the Lite5200B, because the PHY is located at f0003000:01 for the 5200, and at :00 for the 5200B. This was tested on a Lite5200 and a Lite5200B, both booted a kernel via tftp and mounted the root via nfs successfully. Signed-off-by: René Bürgel <r.buergel@unicontrol.de> Acked-by: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: Paul Mackerras <paulus@samba.org>
334 lines
7.7 KiB
Plaintext
334 lines
7.7 KiB
Plaintext
/*
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* Lite5200 board Device Tree Source
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*
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* Copyright 2006-2007 Secret Lab Technologies Ltd.
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* Grant Likely <grant.likely@secretlab.ca>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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/ {
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model = "fsl,lite5200";
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compatible = "fsl,lite5200";
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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PowerPC,5200@0 {
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device_type = "cpu";
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reg = <0>;
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d-cache-line-size = <20>;
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i-cache-line-size = <20>;
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d-cache-size = <4000>; // L1, 16K
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i-cache-size = <4000>; // L1, 16K
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timebase-frequency = <0>; // from bootloader
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bus-frequency = <0>; // from bootloader
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clock-frequency = <0>; // from bootloader
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};
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};
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memory {
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device_type = "memory";
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reg = <00000000 04000000>; // 64MB
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};
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soc5200@f0000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,mpc5200-immr";
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ranges = <0 f0000000 0000c000>;
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reg = <f0000000 00000100>;
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bus-frequency = <0>; // from bootloader
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system-frequency = <0>; // from bootloader
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cdm@200 {
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compatible = "fsl,mpc5200-cdm";
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reg = <200 38>;
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};
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mpc5200_pic: interrupt-controller@500 {
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// 5200 interrupts are encoded into two levels;
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interrupt-controller;
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#interrupt-cells = <3>;
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device_type = "interrupt-controller";
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compatible = "fsl,mpc5200-pic";
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reg = <500 80>;
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};
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timer@600 { // General Purpose Timer
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compatible = "fsl,mpc5200-gpt";
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cell-index = <0>;
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reg = <600 10>;
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interrupts = <1 9 0>;
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interrupt-parent = <&mpc5200_pic>;
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fsl,has-wdt;
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};
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timer@610 { // General Purpose Timer
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compatible = "fsl,mpc5200-gpt";
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cell-index = <1>;
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reg = <610 10>;
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interrupts = <1 a 0>;
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interrupt-parent = <&mpc5200_pic>;
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};
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timer@620 { // General Purpose Timer
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compatible = "fsl,mpc5200-gpt";
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cell-index = <2>;
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reg = <620 10>;
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interrupts = <1 b 0>;
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interrupt-parent = <&mpc5200_pic>;
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};
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timer@630 { // General Purpose Timer
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compatible = "fsl,mpc5200-gpt";
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cell-index = <3>;
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reg = <630 10>;
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interrupts = <1 c 0>;
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interrupt-parent = <&mpc5200_pic>;
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};
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timer@640 { // General Purpose Timer
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compatible = "fsl,mpc5200-gpt";
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cell-index = <4>;
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reg = <640 10>;
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interrupts = <1 d 0>;
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interrupt-parent = <&mpc5200_pic>;
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};
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timer@650 { // General Purpose Timer
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compatible = "fsl,mpc5200-gpt";
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cell-index = <5>;
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reg = <650 10>;
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interrupts = <1 e 0>;
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interrupt-parent = <&mpc5200_pic>;
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};
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timer@660 { // General Purpose Timer
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compatible = "fsl,mpc5200-gpt";
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cell-index = <6>;
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reg = <660 10>;
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interrupts = <1 f 0>;
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interrupt-parent = <&mpc5200_pic>;
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};
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timer@670 { // General Purpose Timer
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compatible = "fsl,mpc5200-gpt";
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cell-index = <7>;
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reg = <670 10>;
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interrupts = <1 10 0>;
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interrupt-parent = <&mpc5200_pic>;
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};
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rtc@800 { // Real time clock
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compatible = "fsl,mpc5200-rtc";
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device_type = "rtc";
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reg = <800 100>;
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interrupts = <1 5 0 1 6 0>;
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interrupt-parent = <&mpc5200_pic>;
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};
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can@900 {
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compatible = "fsl,mpc5200-mscan";
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cell-index = <0>;
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interrupts = <2 11 0>;
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interrupt-parent = <&mpc5200_pic>;
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reg = <900 80>;
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};
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can@980 {
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compatible = "fsl,mpc5200-mscan";
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cell-index = <1>;
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interrupts = <2 12 0>;
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interrupt-parent = <&mpc5200_pic>;
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reg = <980 80>;
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};
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gpio@b00 {
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compatible = "fsl,mpc5200-gpio";
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reg = <b00 40>;
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interrupts = <1 7 0>;
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interrupt-parent = <&mpc5200_pic>;
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};
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gpio@c00 {
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compatible = "fsl,mpc5200-gpio-wkup";
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reg = <c00 40>;
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interrupts = <1 8 0 0 3 0>;
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interrupt-parent = <&mpc5200_pic>;
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};
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spi@f00 {
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compatible = "fsl,mpc5200-spi";
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reg = <f00 20>;
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interrupts = <2 d 0 2 e 0>;
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interrupt-parent = <&mpc5200_pic>;
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};
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usb@1000 {
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compatible = "fsl,mpc5200-ohci","ohci-be";
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reg = <1000 ff>;
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interrupts = <2 6 0>;
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interrupt-parent = <&mpc5200_pic>;
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};
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dma-controller@1200 {
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device_type = "dma-controller";
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compatible = "fsl,mpc5200-bestcomm";
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reg = <1200 80>;
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interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
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3 4 0 3 5 0 3 6 0 3 7 0
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3 8 0 3 9 0 3 a 0 3 b 0
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3 c 0 3 d 0 3 e 0 3 f 0>;
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interrupt-parent = <&mpc5200_pic>;
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};
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xlb@1f00 {
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compatible = "fsl,mpc5200-xlb";
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reg = <1f00 100>;
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};
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serial@2000 { // PSC1
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device_type = "serial";
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compatible = "fsl,mpc5200-psc-uart";
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port-number = <0>; // Logical port assignment
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cell-index = <0>;
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reg = <2000 100>;
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interrupts = <2 1 0>;
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interrupt-parent = <&mpc5200_pic>;
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};
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// PSC2 in ac97 mode example
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//ac97@2200 { // PSC2
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// compatible = "fsl,mpc5200-psc-ac97";
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// cell-index = <1>;
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// reg = <2200 100>;
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// interrupts = <2 2 0>;
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// interrupt-parent = <&mpc5200_pic>;
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//};
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// PSC3 in CODEC mode example
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//i2s@2400 { // PSC3
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// compatible = "fsl,mpc5200-psc-i2s";
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// cell-index = <2>;
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// reg = <2400 100>;
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// interrupts = <2 3 0>;
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// interrupt-parent = <&mpc5200_pic>;
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//};
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// PSC4 in uart mode example
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//serial@2600 { // PSC4
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// device_type = "serial";
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// compatible = "fsl,mpc5200-psc-uart";
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// cell-index = <3>;
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// reg = <2600 100>;
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// interrupts = <2 b 0>;
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// interrupt-parent = <&mpc5200_pic>;
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//};
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// PSC5 in uart mode example
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//serial@2800 { // PSC5
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// device_type = "serial";
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// compatible = "fsl,mpc5200-psc-uart";
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// cell-index = <4>;
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// reg = <2800 100>;
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// interrupts = <2 c 0>;
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// interrupt-parent = <&mpc5200_pic>;
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//};
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// PSC6 in spi mode example
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//spi@2c00 { // PSC6
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// compatible = "fsl,mpc5200-psc-spi";
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// cell-index = <5>;
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// reg = <2c00 100>;
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// interrupts = <2 4 0>;
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// interrupt-parent = <&mpc5200_pic>;
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//};
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ethernet@3000 {
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device_type = "network";
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compatible = "fsl,mpc5200-fec";
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reg = <3000 800>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupts = <2 5 0>;
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interrupt-parent = <&mpc5200_pic>;
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phy-handle = <&phy0>;
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};
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mdio@3000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,mpc5200-mdio";
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reg = <3000 400>; // fec range, since we need to setup fec interrupts
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interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
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interrupt-parent = <&mpc5200_pic>;
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phy0:ethernet-phy@1 {
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device_type = "ethernet-phy";
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reg = <1>;
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};
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};
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ata@3a00 {
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device_type = "ata";
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compatible = "fsl,mpc5200-ata";
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reg = <3a00 100>;
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interrupts = <2 7 0>;
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interrupt-parent = <&mpc5200_pic>;
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};
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i2c@3d00 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,mpc5200-i2c","fsl-i2c";
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cell-index = <0>;
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reg = <3d00 40>;
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interrupts = <2 f 0>;
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interrupt-parent = <&mpc5200_pic>;
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fsl5200-clocking;
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};
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i2c@3d40 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,mpc5200-i2c","fsl-i2c";
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cell-index = <1>;
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reg = <3d40 40>;
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interrupts = <2 10 0>;
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interrupt-parent = <&mpc5200_pic>;
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fsl5200-clocking;
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};
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sram@8000 {
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compatible = "fsl,mpc5200-sram","sram";
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reg = <8000 4000>;
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};
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};
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pci@f0000d00 {
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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device_type = "pci";
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compatible = "fsl,mpc5200-pci";
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reg = <f0000d00 100>;
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interrupt-map-mask = <f800 0 0 7>;
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interrupt-map = <c000 0 0 1 &mpc5200_pic 0 0 3
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c000 0 0 2 &mpc5200_pic 0 0 3
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c000 0 0 3 &mpc5200_pic 0 0 3
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c000 0 0 4 &mpc5200_pic 0 0 3>;
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clock-frequency = <0>; // From boot loader
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interrupts = <2 8 0 2 9 0 2 a 0>;
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interrupt-parent = <&mpc5200_pic>;
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bus-range = <0 0>;
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ranges = <42000000 0 80000000 80000000 0 20000000
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02000000 0 a0000000 a0000000 0 10000000
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01000000 0 00000000 b0000000 0 01000000>;
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};
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};
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