6ee738610f
This adds a drm/kms staging non-API stable driver for GPUs from NVIDIA. This driver is a KMS-based driver and requires a compatible nouveau userspace libdrm and nouveau X.org driver. This driver requires firmware files not available in this kernel tree, interested parties can find them via the nouveau project git archive. This driver is reverse engineered, and is in no way supported by nVidia. Support for nearly the complete range of nvidia hw from nv04->g80 (nv50) is available, and the kms driver should support driving nearly all output types (displayport is under development still) along with supporting suspend/resume. This work is all from the upstream nouveau project found at nouveau.freedesktop.org. The original authors list from nouveau git tree is: Anssi Hannula <anssi.hannula@iki.fi> Ben Skeggs <bskeggs@redhat.com> Francisco Jerez <currojerez@riseup.net> Maarten Maathuis <madman2003@gmail.com> Marcin Kościelnicki <koriakin@0x04.net> Matthew Garrett <mjg@redhat.com> Matt Parnell <mparnell@gmail.com> Patrice Mandin <patmandin@gmail.com> Pekka Paalanen <pq@iki.fi> Xavier Chantry <shiningxc@gmail.com> along with project founder Stephane Marchesin <marchesin@icps.u-strasbg.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
63 lines
1.5 KiB
C
63 lines
1.5 KiB
C
#include "drmP.h"
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#include "drm.h"
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#include "nouveau_drv.h"
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#include "nouveau_drm.h"
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int
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nv40_fb_init(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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uint32_t fb_bar_size, tmp;
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int num_tiles;
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int i;
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/* This is strictly a NV4x register (don't know about NV5x). */
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/* The blob sets these to all kinds of values, and they mess up our setup. */
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/* I got value 0x52802 instead. For some cards the blob even sets it back to 0x1. */
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/* Note: the blob doesn't read this value, so i'm pretty sure this is safe for all cards. */
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/* Any idea what this is? */
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nv_wr32(dev, NV40_PFB_UNK_800, 0x1);
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switch (dev_priv->chipset) {
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case 0x40:
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case 0x45:
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tmp = nv_rd32(dev, NV10_PFB_CLOSE_PAGE2);
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nv_wr32(dev, NV10_PFB_CLOSE_PAGE2, tmp & ~(1 << 15));
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num_tiles = NV10_PFB_TILE__SIZE;
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break;
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case 0x46: /* G72 */
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case 0x47: /* G70 */
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case 0x49: /* G71 */
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case 0x4b: /* G73 */
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case 0x4c: /* C51 (G7X version) */
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num_tiles = NV40_PFB_TILE__SIZE_1;
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break;
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default:
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num_tiles = NV40_PFB_TILE__SIZE_0;
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break;
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}
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fb_bar_size = drm_get_resource_len(dev, 0) - 1;
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switch (dev_priv->chipset) {
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case 0x40:
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for (i = 0; i < num_tiles; i++) {
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nv_wr32(dev, NV10_PFB_TILE(i), 0);
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nv_wr32(dev, NV10_PFB_TLIMIT(i), fb_bar_size);
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}
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break;
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default:
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for (i = 0; i < num_tiles; i++) {
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nv_wr32(dev, NV40_PFB_TILE(i), 0);
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nv_wr32(dev, NV40_PFB_TLIMIT(i), fb_bar_size);
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}
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break;
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}
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return 0;
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}
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void
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nv40_fb_takedown(struct drm_device *dev)
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{
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}
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