9863be598e
Add a load option to intel-rng to allow skipping the FWH detection, necessary in case the BIOS has locked read-only the firmware hub space. Also prevent any attempt to write to firmware space if it cannot be write enabled (apparently caused hangs on some systems not having an FWH and thus also not having a respective RNG). Signed-off-by: Jan Beulich <jbeulich@novell.com> Signed-off-by: Michael Buesch <mb@bu3sch.de> Cc: Jeff Garzik <jeff@garzik.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
386 lines
11 KiB
C
386 lines
11 KiB
C
/*
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* RNG driver for Intel RNGs
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*
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* Copyright 2005 (c) MontaVista Software, Inc.
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*
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* with the majority of the code coming from:
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*
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* Hardware driver for the Intel/AMD/VIA Random Number Generators (RNG)
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* (c) Copyright 2003 Red Hat Inc <jgarzik@redhat.com>
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*
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* derived from
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*
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* Hardware driver for the AMD 768 Random Number Generator (RNG)
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* (c) Copyright 2001 Red Hat Inc <alan@redhat.com>
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*
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* derived from
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*
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* Hardware driver for Intel i810 Random Number Generator (RNG)
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* Copyright 2000,2001 Jeff Garzik <jgarzik@pobox.com>
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* Copyright 2000,2001 Philipp Rumpf <prumpf@mandrakesoft.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/hw_random.h>
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#include <asm/io.h>
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#define PFX KBUILD_MODNAME ": "
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/*
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* RNG registers
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*/
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#define INTEL_RNG_HW_STATUS 0
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#define INTEL_RNG_PRESENT 0x40
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#define INTEL_RNG_ENABLED 0x01
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#define INTEL_RNG_STATUS 1
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#define INTEL_RNG_DATA_PRESENT 0x01
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#define INTEL_RNG_DATA 2
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/*
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* Magic address at which Intel PCI bridges locate the RNG
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*/
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#define INTEL_RNG_ADDR 0xFFBC015F
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#define INTEL_RNG_ADDR_LEN 3
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/*
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* LPC bridge PCI config space registers
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*/
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#define FWH_DEC_EN1_REG_OLD 0xe3
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#define FWH_DEC_EN1_REG_NEW 0xd9 /* high byte of 16-bit register */
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#define FWH_F8_EN_MASK 0x80
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#define BIOS_CNTL_REG_OLD 0x4e
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#define BIOS_CNTL_REG_NEW 0xdc
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#define BIOS_CNTL_WRITE_ENABLE_MASK 0x01
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#define BIOS_CNTL_LOCK_ENABLE_MASK 0x02
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/*
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* Magic address at which Intel Firmware Hubs get accessed
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*/
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#define INTEL_FWH_ADDR 0xffff0000
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#define INTEL_FWH_ADDR_LEN 2
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/*
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* Intel Firmware Hub command codes (write to any address inside the device)
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*/
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#define INTEL_FWH_RESET_CMD 0xff /* aka READ_ARRAY */
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#define INTEL_FWH_READ_ID_CMD 0x90
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/*
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* Intel Firmware Hub Read ID command result addresses
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*/
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#define INTEL_FWH_MANUFACTURER_CODE_ADDRESS 0x000000
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#define INTEL_FWH_DEVICE_CODE_ADDRESS 0x000001
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/*
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* Intel Firmware Hub Read ID command result values
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*/
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#define INTEL_FWH_MANUFACTURER_CODE 0x89
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#define INTEL_FWH_DEVICE_CODE_8M 0xac
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#define INTEL_FWH_DEVICE_CODE_4M 0xad
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/*
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* Data for PCI driver interface
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*
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* This data only exists for exporting the supported
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* PCI ids via MODULE_DEVICE_TABLE. We do not actually
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* register a pci_driver, because someone else might one day
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* want to register another driver on the same PCI id.
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*/
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static const struct pci_device_id pci_tbl[] = {
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/* AA
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{ 0x8086, 0x2418, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, }, */
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{ 0x8086, 0x2410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, }, /* AA */
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/* AB
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{ 0x8086, 0x2428, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, }, */
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{ 0x8086, 0x2420, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, }, /* AB */
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/* ??
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{ 0x8086, 0x2430, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, }, */
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/* BAM, CAM, DBM, FBM, GxM
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{ 0x8086, 0x2448, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, }, */
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{ 0x8086, 0x244c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, }, /* BAM */
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{ 0x8086, 0x248c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, }, /* CAM */
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{ 0x8086, 0x24cc, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, }, /* DBM */
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{ 0x8086, 0x2641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, }, /* FBM */
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{ 0x8086, 0x27b9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, }, /* GxM */
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{ 0x8086, 0x27bd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, }, /* GxM DH */
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/* BA, CA, DB, Ex, 6300, Fx, 631x/632x, Gx
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{ 0x8086, 0x244e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, }, */
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{ 0x8086, 0x2440, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, }, /* BA */
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{ 0x8086, 0x2480, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, }, /* CA */
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{ 0x8086, 0x24c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, }, /* DB */
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{ 0x8086, 0x24d0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, }, /* Ex */
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{ 0x8086, 0x25a1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, }, /* 6300 */
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{ 0x8086, 0x2640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, }, /* Fx */
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{ 0x8086, 0x2670, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, }, /* 631x/632x */
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{ 0x8086, 0x2671, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, }, /* 631x/632x */
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{ 0x8086, 0x2672, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, }, /* 631x/632x */
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{ 0x8086, 0x2673, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, }, /* 631x/632x */
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{ 0x8086, 0x2674, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, }, /* 631x/632x */
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{ 0x8086, 0x2675, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, }, /* 631x/632x */
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{ 0x8086, 0x2676, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, }, /* 631x/632x */
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{ 0x8086, 0x2677, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, }, /* 631x/632x */
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{ 0x8086, 0x2678, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, }, /* 631x/632x */
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{ 0x8086, 0x2679, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, }, /* 631x/632x */
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{ 0x8086, 0x267a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, }, /* 631x/632x */
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{ 0x8086, 0x267b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, }, /* 631x/632x */
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{ 0x8086, 0x267c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, }, /* 631x/632x */
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{ 0x8086, 0x267d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, }, /* 631x/632x */
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{ 0x8086, 0x267e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, }, /* 631x/632x */
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{ 0x8086, 0x267f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, }, /* 631x/632x */
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{ 0x8086, 0x27b8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, }, /* Gx */
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/* E
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{ 0x8086, 0x245e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, }, */
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{ 0x8086, 0x2450, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, }, /* E */
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{ 0, }, /* terminate list */
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};
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MODULE_DEVICE_TABLE(pci, pci_tbl);
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static __initdata int no_fwh_detect;
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module_param(no_fwh_detect, int, 0);
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MODULE_PARM_DESC(no_fwh_detect, "Skip FWH detection:\n"
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" positive value - skip if FWH space locked read-only\n"
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" negative value - skip always");
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static inline u8 hwstatus_get(void __iomem *mem)
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{
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return readb(mem + INTEL_RNG_HW_STATUS);
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}
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static inline u8 hwstatus_set(void __iomem *mem,
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u8 hw_status)
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{
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writeb(hw_status, mem + INTEL_RNG_HW_STATUS);
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return hwstatus_get(mem);
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}
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static int intel_rng_data_present(struct hwrng *rng)
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{
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void __iomem *mem = (void __iomem *)rng->priv;
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return !!(readb(mem + INTEL_RNG_STATUS) & INTEL_RNG_DATA_PRESENT);
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}
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static int intel_rng_data_read(struct hwrng *rng, u32 *data)
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{
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void __iomem *mem = (void __iomem *)rng->priv;
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*data = readb(mem + INTEL_RNG_DATA);
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return 1;
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}
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static int intel_rng_init(struct hwrng *rng)
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{
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void __iomem *mem = (void __iomem *)rng->priv;
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u8 hw_status;
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int err = -EIO;
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hw_status = hwstatus_get(mem);
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/* turn RNG h/w on, if it's off */
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if ((hw_status & INTEL_RNG_ENABLED) == 0)
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hw_status = hwstatus_set(mem, hw_status | INTEL_RNG_ENABLED);
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if ((hw_status & INTEL_RNG_ENABLED) == 0) {
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printk(KERN_ERR PFX "cannot enable RNG, aborting\n");
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goto out;
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}
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err = 0;
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out:
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return err;
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}
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static void intel_rng_cleanup(struct hwrng *rng)
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{
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void __iomem *mem = (void __iomem *)rng->priv;
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u8 hw_status;
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hw_status = hwstatus_get(mem);
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if (hw_status & INTEL_RNG_ENABLED)
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hwstatus_set(mem, hw_status & ~INTEL_RNG_ENABLED);
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else
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printk(KERN_WARNING PFX "unusual: RNG already disabled\n");
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}
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static struct hwrng intel_rng = {
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.name = "intel",
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.init = intel_rng_init,
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.cleanup = intel_rng_cleanup,
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.data_present = intel_rng_data_present,
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.data_read = intel_rng_data_read,
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};
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#ifdef CONFIG_SMP
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static char __initdata waitflag;
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static void __init intel_init_wait(void *unused)
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{
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while (waitflag)
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cpu_relax();
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}
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#endif
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static int __init mod_init(void)
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{
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int err = -ENODEV;
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unsigned i;
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struct pci_dev *dev = NULL;
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void __iomem *mem;
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unsigned long flags;
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u8 bios_cntl_off, fwh_dec_en1_off;
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u8 bios_cntl_val = 0xff, fwh_dec_en1_val = 0xff;
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u8 hw_status, mfc, dvc;
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for (i = 0; !dev && pci_tbl[i].vendor; ++i)
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dev = pci_get_device(pci_tbl[i].vendor, pci_tbl[i].device, NULL);
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if (!dev)
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goto out; /* Device not found. */
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if (no_fwh_detect < 0) {
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pci_dev_put(dev);
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goto fwh_done;
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}
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/* Check for Intel 82802 */
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if (dev->device < 0x2640) {
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fwh_dec_en1_off = FWH_DEC_EN1_REG_OLD;
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bios_cntl_off = BIOS_CNTL_REG_OLD;
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} else {
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fwh_dec_en1_off = FWH_DEC_EN1_REG_NEW;
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bios_cntl_off = BIOS_CNTL_REG_NEW;
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}
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pci_read_config_byte(dev, fwh_dec_en1_off, &fwh_dec_en1_val);
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pci_read_config_byte(dev, bios_cntl_off, &bios_cntl_val);
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if ((bios_cntl_val &
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(BIOS_CNTL_LOCK_ENABLE_MASK|BIOS_CNTL_WRITE_ENABLE_MASK))
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== BIOS_CNTL_LOCK_ENABLE_MASK) {
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static __initdata /*const*/ char warning[] =
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KERN_WARNING PFX "Firmware space is locked read-only. If you can't or\n"
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KERN_WARNING PFX "don't want to disable this in firmware setup, and if\n"
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KERN_WARNING PFX "you are certain that your system has a functional\n"
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KERN_WARNING PFX "RNG, try using the 'no_fwh_detect' option.\n";
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pci_dev_put(dev);
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if (no_fwh_detect)
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goto fwh_done;
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printk(warning);
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err = -EBUSY;
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goto out;
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}
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mem = ioremap_nocache(INTEL_FWH_ADDR, INTEL_FWH_ADDR_LEN);
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if (mem == NULL) {
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pci_dev_put(dev);
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err = -EBUSY;
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goto out;
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}
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/*
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* Since the BIOS code/data is going to disappear from its normal
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* location with the Read ID command, all activity on the system
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* must be stopped until the state is back to normal.
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*/
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#ifdef CONFIG_SMP
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set_mb(waitflag, 1);
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if (smp_call_function(intel_init_wait, NULL, 1, 0) != 0) {
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set_mb(waitflag, 0);
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pci_dev_put(dev);
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printk(KERN_ERR PFX "cannot run on all processors\n");
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err = -EAGAIN;
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goto err_unmap;
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}
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#endif
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local_irq_save(flags);
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if (!(fwh_dec_en1_val & FWH_F8_EN_MASK))
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pci_write_config_byte(dev,
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fwh_dec_en1_off,
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fwh_dec_en1_val | FWH_F8_EN_MASK);
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if (!(bios_cntl_val & BIOS_CNTL_WRITE_ENABLE_MASK))
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pci_write_config_byte(dev,
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bios_cntl_off,
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bios_cntl_val | BIOS_CNTL_WRITE_ENABLE_MASK);
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writeb(INTEL_FWH_RESET_CMD, mem);
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writeb(INTEL_FWH_READ_ID_CMD, mem);
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mfc = readb(mem + INTEL_FWH_MANUFACTURER_CODE_ADDRESS);
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dvc = readb(mem + INTEL_FWH_DEVICE_CODE_ADDRESS);
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writeb(INTEL_FWH_RESET_CMD, mem);
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if (!(bios_cntl_val &
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(BIOS_CNTL_LOCK_ENABLE_MASK|BIOS_CNTL_WRITE_ENABLE_MASK)))
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pci_write_config_byte(dev, bios_cntl_off, bios_cntl_val);
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if (!(fwh_dec_en1_val & FWH_F8_EN_MASK))
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pci_write_config_byte(dev, fwh_dec_en1_off, fwh_dec_en1_val);
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local_irq_restore(flags);
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#ifdef CONFIG_SMP
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/* Tell other CPUs to resume. */
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set_mb(waitflag, 0);
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#endif
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iounmap(mem);
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pci_dev_put(dev);
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if (mfc != INTEL_FWH_MANUFACTURER_CODE ||
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(dvc != INTEL_FWH_DEVICE_CODE_8M &&
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dvc != INTEL_FWH_DEVICE_CODE_4M)) {
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printk(KERN_ERR PFX "FWH not detected\n");
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err = -ENODEV;
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goto out;
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}
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fwh_done:
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err = -ENOMEM;
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mem = ioremap(INTEL_RNG_ADDR, INTEL_RNG_ADDR_LEN);
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if (!mem)
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goto out;
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intel_rng.priv = (unsigned long)mem;
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/* Check for Random Number Generator */
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err = -ENODEV;
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hw_status = hwstatus_get(mem);
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if ((hw_status & INTEL_RNG_PRESENT) == 0)
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goto err_unmap;
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printk(KERN_INFO "Intel 82802 RNG detected\n");
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err = hwrng_register(&intel_rng);
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if (err) {
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printk(KERN_ERR PFX "RNG registering failed (%d)\n",
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err);
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goto err_unmap;
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}
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out:
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return err;
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err_unmap:
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iounmap(mem);
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goto out;
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}
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static void __exit mod_exit(void)
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{
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void __iomem *mem = (void __iomem *)intel_rng.priv;
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hwrng_unregister(&intel_rng);
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iounmap(mem);
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}
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subsys_initcall(mod_init);
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module_exit(mod_exit);
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MODULE_DESCRIPTION("H/W RNG driver for Intel chipsets");
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MODULE_LICENSE("GPL");
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