98c5584cfc
This also cleans up tsb_context_switch(). The assembler routine is now __tsb_context_switch() and the former is an inline function that picks out the bits from the mm_struct and passes it into the assembler code as arguments. setup_tsb_parms() computes the locked TLB entry to map the TSB. Later when we support using the physical address quad load instructions of Cheetah+ and later, we'll simply use the physical address for the TSB register value and set the map virtual and PTE both to zero. Signed-off-by: David S. Miller <davem@davemloft.net>
166 lines
5.6 KiB
C
166 lines
5.6 KiB
C
#ifndef _SPARC64_TSB_H
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#define _SPARC64_TSB_H
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/* The sparc64 TSB is similar to the powerpc hashtables. It's a
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* power-of-2 sized table of TAG/PTE pairs. The cpu precomputes
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* pointers into this table for 8K and 64K page sizes, and also a
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* comparison TAG based upon the virtual address and context which
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* faults.
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*
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* TLB miss trap handler software does the actual lookup via something
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* of the form:
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*
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* ldxa [%g0] ASI_{D,I}MMU_TSB_8KB_PTR, %g1
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* ldxa [%g0] ASI_{D,I}MMU, %g6
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* ldda [%g1] ASI_NUCLEUS_QUAD_LDD, %g4
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* cmp %g4, %g6
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* bne,pn %xcc, tsb_miss_{d,i}tlb
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* mov FAULT_CODE_{D,I}TLB, %g3
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* stxa %g5, [%g0] ASI_{D,I}TLB_DATA_IN
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* retry
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*
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*
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* Each 16-byte slot of the TSB is the 8-byte tag and then the 8-byte
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* PTE. The TAG is of the same layout as the TLB TAG TARGET mmu
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* register which is:
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*
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* -------------------------------------------------
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* | - | CONTEXT | - | VADDR bits 63:22 |
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* -------------------------------------------------
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* 63 61 60 48 47 42 41 0
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*
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* Like the powerpc hashtables we need to use locking in order to
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* synchronize while we update the entries. PTE updates need locking
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* as well.
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*
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* We need to carefully choose a lock bits for the TSB entry. We
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* choose to use bit 47 in the tag. Also, since we never map anything
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* at page zero in context zero, we use zero as an invalid tag entry.
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* When the lock bit is set, this forces a tag comparison failure.
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*
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* Currently, we allocate an 8K TSB per-process and we use it for both
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* I-TLB and D-TLB misses. Perhaps at some point we'll add code that
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* monitors the number of active pages in the process as we get
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* major/minor faults, and grow the TSB in response. The only trick
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* in implementing that is synchronizing the freeing of the old TSB
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* wrt. parallel TSB updates occuring on other processors. On
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* possible solution is to use RCU for the freeing of the TSB.
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*/
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#define TSB_TAG_LOCK (1 << (47 - 32))
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#define TSB_MEMBAR membar #StoreStore
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#define TSB_LOCK_TAG(TSB, REG1, REG2) \
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99: lduwa [TSB] ASI_N, REG1; \
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sethi %hi(TSB_TAG_LOCK), REG2;\
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andcc REG1, REG2, %g0; \
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bne,pn %icc, 99b; \
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nop; \
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casa [TSB] ASI_N, REG1, REG2;\
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cmp REG1, REG2; \
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bne,pn %icc, 99b; \
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nop; \
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TSB_MEMBAR
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#define TSB_WRITE(TSB, TTE, TAG) \
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stx TTE, [TSB + 0x08]; \
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TSB_MEMBAR; \
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stx TAG, [TSB + 0x00];
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/* Do a kernel page table walk. Leaves physical PTE pointer in
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* REG1. Jumps to FAIL_LABEL on early page table walk termination.
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* VADDR will not be clobbered, but REG2 will.
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*/
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#define KERN_PGTABLE_WALK(VADDR, REG1, REG2, FAIL_LABEL) \
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sethi %hi(swapper_pg_dir), REG1; \
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or REG1, %lo(swapper_pg_dir), REG1; \
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sllx VADDR, 64 - (PGDIR_SHIFT + PGDIR_BITS), REG2; \
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srlx REG2, 64 - PAGE_SHIFT, REG2; \
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andn REG2, 0x3, REG2; \
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lduw [REG1 + REG2], REG1; \
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brz,pn REG1, FAIL_LABEL; \
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sllx VADDR, 64 - (PMD_SHIFT + PMD_BITS), REG2; \
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srlx REG2, 64 - PAGE_SHIFT, REG2; \
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sllx REG1, 11, REG1; \
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andn REG2, 0x3, REG2; \
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lduwa [REG1 + REG2] ASI_PHYS_USE_EC, REG1; \
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brz,pn REG1, FAIL_LABEL; \
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sllx VADDR, 64 - PMD_SHIFT, REG2; \
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srlx REG2, 64 - PAGE_SHIFT, REG2; \
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sllx REG1, 11, REG1; \
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andn REG2, 0x7, REG2; \
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add REG1, REG2, REG1;
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/* Do a user page table walk in MMU globals. Leaves physical PTE
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* pointer in REG1. Jumps to FAIL_LABEL on early page table walk
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* termination. Physical base of page tables is in PHYS_PGD which
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* will not be modified.
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*
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* VADDR will not be clobbered, but REG1 and REG2 will.
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*/
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#define USER_PGTABLE_WALK_TL1(VADDR, PHYS_PGD, REG1, REG2, FAIL_LABEL) \
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sllx VADDR, 64 - (PGDIR_SHIFT + PGDIR_BITS), REG2; \
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srlx REG2, 64 - PAGE_SHIFT, REG2; \
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andn REG2, 0x3, REG2; \
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lduwa [PHYS_PGD + REG2] ASI_PHYS_USE_EC, REG1; \
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brz,pn REG1, FAIL_LABEL; \
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sllx VADDR, 64 - (PMD_SHIFT + PMD_BITS), REG2; \
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srlx REG2, 64 - PAGE_SHIFT, REG2; \
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sllx REG1, 11, REG1; \
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andn REG2, 0x3, REG2; \
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lduwa [REG1 + REG2] ASI_PHYS_USE_EC, REG1; \
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brz,pn REG1, FAIL_LABEL; \
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sllx VADDR, 64 - PMD_SHIFT, REG2; \
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srlx REG2, 64 - PAGE_SHIFT, REG2; \
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sllx REG1, 11, REG1; \
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andn REG2, 0x7, REG2; \
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add REG1, REG2, REG1;
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/* Lookup a OBP mapping on VADDR in the prom_trans[] table at TL>0.
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* If no entry is found, FAIL_LABEL will be branched to. On success
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* the resulting PTE value will be left in REG1. VADDR is preserved
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* by this routine.
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*/
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#define OBP_TRANS_LOOKUP(VADDR, REG1, REG2, REG3, FAIL_LABEL) \
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sethi %hi(prom_trans), REG1; \
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or REG1, %lo(prom_trans), REG1; \
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97: ldx [REG1 + 0x00], REG2; \
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brz,pn REG2, FAIL_LABEL; \
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nop; \
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ldx [REG1 + 0x08], REG3; \
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add REG2, REG3, REG3; \
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cmp REG2, VADDR; \
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bgu,pt %xcc, 98f; \
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cmp VADDR, REG3; \
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bgeu,pt %xcc, 98f; \
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ldx [REG1 + 0x10], REG3; \
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sub VADDR, REG2, REG2; \
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ba,pt %xcc, 99f; \
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add REG3, REG2, REG1; \
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98: ba,pt %xcc, 97b; \
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add REG1, (3 * 8), REG1; \
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99:
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/* Do a kernel TSB lookup at tl>0 on VADDR+TAG, branch to OK_LABEL
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* on TSB hit. REG1, REG2, REG3, and REG4 are used as temporaries
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* and the found TTE will be left in REG1. REG3 and REG4 must
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* be an even/odd pair of registers.
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*
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* VADDR and TAG will be preserved and not clobbered by this macro.
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*/
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/* XXX non-8K base page size support... */
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#define KERN_TSB_LOOKUP_TL1(VADDR, TAG, REG1, REG2, REG3, REG4, OK_LABEL) \
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sethi %hi(swapper_tsb), REG1; \
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or REG1, %lo(swapper_tsb), REG1; \
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srlx VADDR, 13, REG2; \
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and REG2, (512 - 1), REG2; \
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sllx REG2, 4, REG2; \
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add REG1, REG2, REG2; \
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ldda [REG2] ASI_NUCLEUS_QUAD_LDD, REG3; \
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cmp REG3, TAG; \
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be,a,pt %xcc, OK_LABEL; \
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mov REG4, REG1;
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#endif /* !(_SPARC64_TSB_H) */
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