999304be11
This patch adds setup code for Samsung OneNAND controller driver. The driver needs to be aware on which SoC it is running, so the actual device id is being changed in cpu init code. S3C64xx SoCs have 2 OneNAND controllers while S5PC100 and S5PC110 has only one. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> [ben-linux@fluff.org: sort map.h entries] Signed-off-by: Ben Dooks <ben-linux@fluff.org>
86 lines
2.1 KiB
C
86 lines
2.1 KiB
C
/* linux/arch/arm/mach-s5pv210/include/mach/map.h
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*
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* Copyright (c) 2010 Samsung Electronics Co., Ltd.
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* http://www.samsung.com/
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*
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* S5PV210 - Memory map definitions
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_ARCH_MAP_H
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#define __ASM_ARCH_MAP_H __FILE__
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#include <plat/map-base.h>
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#include <plat/map-s5p.h>
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#define S5PC110_PA_ONENAND (0xB0000000)
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#define S5PC110_PA_ONENAND_DMA (0xB0600000)
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#define S5PV210_PA_CHIPID (0xE0000000)
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#define S5P_PA_CHIPID S5PV210_PA_CHIPID
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#define S5PV210_PA_SYSCON (0xE0100000)
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#define S5P_PA_SYSCON S5PV210_PA_SYSCON
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#define S5PV210_PA_GPIO (0xE0200000)
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#define S5P_PA_GPIO S5PV210_PA_GPIO
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#define S5PV210_PA_IIC0 (0xE1800000)
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#define S5PV210_PA_TIMER (0xE2500000)
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#define S5P_PA_TIMER S5PV210_PA_TIMER
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#define S5PV210_PA_SYSTIMER (0xE2600000)
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#define S5PV210_PA_UART (0xE2900000)
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#define S5P_PA_UART0 (S5PV210_PA_UART + 0x0)
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#define S5P_PA_UART1 (S5PV210_PA_UART + 0x400)
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#define S5P_PA_UART2 (S5PV210_PA_UART + 0x800)
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#define S5P_PA_UART3 (S5PV210_PA_UART + 0xC00)
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#define S5P_SZ_UART SZ_256
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#define S5PV210_PA_SROMC (0xE8000000)
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#define S5PV210_PA_MDMA 0xFA200000
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#define S5PV210_PA_PDMA0 0xE0900000
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#define S5PV210_PA_PDMA1 0xE0A00000
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#define S5PV210_PA_VIC0 (0xF2000000)
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#define S5P_PA_VIC0 S5PV210_PA_VIC0
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#define S5PV210_PA_VIC1 (0xF2100000)
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#define S5P_PA_VIC1 S5PV210_PA_VIC1
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#define S5PV210_PA_VIC2 (0xF2200000)
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#define S5P_PA_VIC2 S5PV210_PA_VIC2
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#define S5PV210_PA_VIC3 (0xF2300000)
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#define S5P_PA_VIC3 S5PV210_PA_VIC3
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#define S5PV210_PA_SDRAM (0x20000000)
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#define S5P_PA_SDRAM S5PV210_PA_SDRAM
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/* I2S */
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#define S5PV210_PA_IIS0 0xEEE30000
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#define S5PV210_PA_IIS1 0xE2100000
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#define S5PV210_PA_IIS2 0xE2A00000
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/* PCM */
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#define S5PV210_PA_PCM0 0xE2300000
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#define S5PV210_PA_PCM1 0xE1200000
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#define S5PV210_PA_PCM2 0xE2B00000
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/* AC97 */
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#define S5PV210_PA_AC97 0xE2200000
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/* compatibiltiy defines. */
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#define S3C_PA_UART S5PV210_PA_UART
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#define S3C_PA_IIC S5PV210_PA_IIC0
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#endif /* __ASM_ARCH_MAP_H */
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