a153e31abb
SPI bus clocks can be avoided passing through platform data as spi driver is getting the bus clock using the generic clock connection id registered via clkdev. Signed-off-by: Padmavathi Venna <padma.v@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
74 lines
2.5 KiB
C
74 lines
2.5 KiB
C
/* linux/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
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*
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* Copyright (C) 2009 Samsung Electronics Ltd.
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* Jaswinder Singh <jassi.brar@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __S3C64XX_PLAT_SPI_H
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#define __S3C64XX_PLAT_SPI_H
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/**
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* struct s3c64xx_spi_csinfo - ChipSelect description
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* @fb_delay: Slave specific feedback delay.
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* Refer to FB_CLK_SEL register definition in SPI chapter.
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* @line: Custom 'identity' of the CS line.
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* @set_level: CS line control.
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*
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* This is per SPI-Slave Chipselect information.
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* Allocate and initialize one in machine init code and make the
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* spi_board_info.controller_data point to it.
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*/
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struct s3c64xx_spi_csinfo {
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u8 fb_delay;
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unsigned line;
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void (*set_level)(unsigned line_id, int lvl);
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};
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/**
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* struct s3c64xx_spi_info - SPI Controller defining structure
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* @src_clk_nr: Clock source index for the CLK_CFG[SPI_CLKSEL] field.
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* @clk_from_cmu: If the SPI clock/prescalar control block is present
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* by the platform's clock-management-unit and not in SPI controller.
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* @num_cs: Number of CS this controller emulates.
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* @cfg_gpio: Configure pins for this SPI controller.
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* @fifo_lvl_mask: All tx fifo_lvl fields start at offset-6
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* @rx_lvl_offset: Depends on tx fifo_lvl field and bus number
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* @high_speed: If the controller supports HIGH_SPEED_EN bit
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* @tx_st_done: Depends on tx fifo_lvl field
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*/
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struct s3c64xx_spi_info {
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int src_clk_nr;
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bool clk_from_cmu;
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int num_cs;
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int (*cfg_gpio)(struct platform_device *pdev);
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/* Following two fields are for future compatibility */
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int fifo_lvl_mask;
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int rx_lvl_offset;
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int high_speed;
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int tx_st_done;
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};
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/**
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* s3c64xx_spi_set_info - SPI Controller configure callback by the board
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* initialization code.
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* @cntrlr: SPI controller number the configuration is for.
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* @src_clk_nr: Clock the SPI controller is to use to generate SPI clocks.
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* @num_cs: Number of elements in the 'cs' array.
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*
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* Call this from machine init code for each SPI Controller that
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* has some chips attached to it.
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*/
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extern void s3c64xx_spi_set_info(int cntrlr, int src_clk_nr, int num_cs);
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extern void s5pc100_spi_set_info(int cntrlr, int src_clk_nr, int num_cs);
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extern void s5pv210_spi_set_info(int cntrlr, int src_clk_nr, int num_cs);
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extern void s5p64x0_spi_set_info(int cntrlr, int src_clk_nr, int num_cs);
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#endif /* __S3C64XX_PLAT_SPI_H */
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