1fb3726cf3
The timer irqs statically mapped from linux irq numbers 11 to 15 are moved to the end of the statically mapped linux irq space. The GIC PPI and SPI interrupts are relocated to start from 16 and 32 of the linux irq space. This is a required to add device tree support for GIC and Interrupt combiner for EXYNOS4. A new macro 'IRQ_TIMER_BASE' specifies a platform specific base of the linux virq number for the timer interrupts. For exynos4, this base is set to end of the linux virq space. For the other S5P platforms, the existing base '11' is retained. Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
82 lines
2.6 KiB
C
82 lines
2.6 KiB
C
/* linux/arch/arm/plat-samsung/include/plat/irqs.h
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*
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* Copyright (c) 2009 Samsung Electronics Co., Ltd.
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* http://www.samsung.com/
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*
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* S5P Common IRQ support
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __PLAT_SAMSUNG_IRQS_H
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#define __PLAT_SAMSUNG_IRQS_H __FILE__
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/* we keep the first set of CPU IRQs out of the range of
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* the ISA space, so that the PC104 has them to itself
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* and we don't end up having to do horrible things to the
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* standard ISA drivers....
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*
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* note, since we're using the VICs, our start must be a
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* mulitple of 32 to allow the common code to work
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*/
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#define S5P_IRQ_OFFSET (32)
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#define S5P_IRQ(x) ((x) + S5P_IRQ_OFFSET)
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#define S5P_VIC0_BASE S5P_IRQ(0)
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#define S5P_VIC1_BASE S5P_IRQ(32)
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#define S5P_VIC2_BASE S5P_IRQ(64)
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#define S5P_VIC3_BASE S5P_IRQ(96)
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#define VIC_BASE(x) (S5P_VIC0_BASE + ((x)*32))
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#define IRQ_VIC0_BASE S5P_VIC0_BASE
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#define IRQ_VIC1_BASE S5P_VIC1_BASE
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#define IRQ_VIC2_BASE S5P_VIC2_BASE
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/* VIC based IRQs */
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#define S5P_IRQ_VIC0(x) (S5P_VIC0_BASE + (x))
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#define S5P_IRQ_VIC1(x) (S5P_VIC1_BASE + (x))
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#define S5P_IRQ_VIC2(x) (S5P_VIC2_BASE + (x))
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#define S5P_IRQ_VIC3(x) (S5P_VIC3_BASE + (x))
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#define S5P_TIMER_IRQ(x) (IRQ_TIMER_BASE + (x))
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#define IRQ_TIMER0 S5P_TIMER_IRQ(0)
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#define IRQ_TIMER1 S5P_TIMER_IRQ(1)
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#define IRQ_TIMER2 S5P_TIMER_IRQ(2)
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#define IRQ_TIMER3 S5P_TIMER_IRQ(3)
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#define IRQ_TIMER4 S5P_TIMER_IRQ(4)
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#define IRQ_TIMER_COUNT (5)
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#define IRQ_EINT(x) ((x) < 16 ? ((x) + S5P_EINT_BASE1) \
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: ((x) - 16 + S5P_EINT_BASE2))
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#define EINT_OFFSET(irq) ((irq) < S5P_EINT_BASE2 ? \
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((irq) - S5P_EINT_BASE1) : \
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((irq) + 16 - S5P_EINT_BASE2))
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#define IRQ_EINT_BIT(x) EINT_OFFSET(x)
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/* Typically only a few gpio chips require gpio interrupt support.
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To avoid memory waste irq descriptors are allocated only for
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S5P_GPIOINT_GROUP_COUNT chips, each with total number of
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S5P_GPIOINT_GROUP_SIZE pins/irqs. Each GPIOINT group can be assiged
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to any gpio chip with the s5p_register_gpio_interrupt() function */
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#define S5P_GPIOINT_GROUP_COUNT 4
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#define S5P_GPIOINT_GROUP_SIZE 8
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#define S5P_GPIOINT_COUNT (S5P_GPIOINT_GROUP_COUNT * S5P_GPIOINT_GROUP_SIZE)
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/* IRQ types common for all s5p platforms */
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#define S5P_IRQ_TYPE_LEVEL_LOW (0x00)
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#define S5P_IRQ_TYPE_LEVEL_HIGH (0x01)
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#define S5P_IRQ_TYPE_EDGE_FALLING (0x02)
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#define S5P_IRQ_TYPE_EDGE_RISING (0x03)
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#define S5P_IRQ_TYPE_EDGE_BOTH (0x04)
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#endif /* __PLAT_SAMSUNG_IRQS_H */
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