66d29985fa
Create a common NMI and reset handler in smpboot.S and use this for both XLR and XLP. In the earlier code, the woken up CPUs would busy wait until released, switch this to wakeup by NMI. The initial wakeup code or XLR and XLP are differ since they are started from different bootloaders (XLP from u-boot and XLR from netlogic bootloader). But in both platforms the woken up CPUs wait and are released by sending an NMI. Add support for starting XLR and XLP in 1/2/4 threads per core. Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2970/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
103 lines
3.3 KiB
C
103 lines
3.3 KiB
C
/*
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* Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
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* reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the NetLogic
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* license below:
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/threads.h>
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#include <asm/asm.h>
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#include <asm/asm-offsets.h>
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#include <asm/mipsregs.h>
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#include <asm/addrspace.h>
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#include <asm/string.h>
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#include <asm/netlogic/haldefs.h>
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#include <asm/netlogic/common.h>
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#include <asm/netlogic/mips-extns.h>
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#include <asm/netlogic/xlp-hal/iomap.h>
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#include <asm/netlogic/xlp-hal/pic.h>
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#include <asm/netlogic/xlp-hal/xlp.h>
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#include <asm/netlogic/xlp-hal/sys.h>
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static void xlp_enable_secondary_cores(void)
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{
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uint32_t core, value, coremask, syscoremask;
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int count;
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/* read cores in reset from SYS block */
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syscoremask = nlm_read_sys_reg(nlm_sys_base, SYS_CPU_RESET);
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/* update user specified */
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nlm_coremask = nlm_coremask & (syscoremask | 1);
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for (core = 1; core < 8; core++) {
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coremask = 1 << core;
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if ((nlm_coremask & coremask) == 0)
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continue;
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/* Enable CPU clock */
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value = nlm_read_sys_reg(nlm_sys_base, SYS_CORE_DFS_DIS_CTRL);
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value &= ~coremask;
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nlm_write_sys_reg(nlm_sys_base, SYS_CORE_DFS_DIS_CTRL, value);
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/* Remove CPU Reset */
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value = nlm_read_sys_reg(nlm_sys_base, SYS_CPU_RESET);
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value &= ~coremask;
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nlm_write_sys_reg(nlm_sys_base, SYS_CPU_RESET, value);
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/* Poll for CPU to mark itself coherent */
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count = 100000;
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do {
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value = nlm_read_sys_reg(nlm_sys_base,
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SYS_CPU_NONCOHERENT_MODE);
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} while ((value & coremask) != 0 && count-- > 0);
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if (count == 0)
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pr_err("Failed to enable core %d\n", core);
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}
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}
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void xlp_wakeup_secondary_cpus(void)
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{
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/*
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* In case of u-boot, the secondaries are in reset
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* first wakeup core 0 threads
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*/
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xlp_boot_core0_siblings();
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/* now get other cores out of reset */
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xlp_enable_secondary_cores();
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}
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